Visible to Intel only — GUID: GUID-3F85A498-ACD4-4D15-8CD9-218A85D78F13
Visible to Intel only — GUID: GUID-3F85A498-ACD4-4D15-8CD9-218A85D78F13
IP core Reset Behavior
For your IP core, the reset assertion can be asynchronous but the reset deassertion must be synchronous.
The reset assertion and deassertion behavior can be generated from an asynchronous reset input by using reset synchronization. Add reset synchronization to your IP core with Platform Designer when you integrate your IP into a system.
For information about integrating your IP core into a system, refer to Integrating Your IP Into a System.
For an example of adding reset synchronization, refer to the Platform Designer Sample example design.
Synchronizers are implemented to minimize synchronization failures due to metastability in asynchronous signal transfers. For more information about metastability, refer to "Managing Metastability with the Quartus® Prime Software" in Quartus® Prime Pro Edition User Guide: Design Recommendations.
When the reset is asserted, the IP core holds its busy signal high and its done signal low. After the reset is deasserted, the IP core holds its busy signal high until the IP core is ready to accept the next invocation. All IP core interfaces (agents, hosts, and streams) are ready only after the IP core busy signal is low.