Developer Guide

Intel® oneAPI DPC++/C++ Compiler Handbook for FPGAs

ID 785441
Date 10/24/2024
Public
Document Table of Contents

Document Revision History for the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs

Date Release Version Changes
October 2024 2025.0
  • Maintenance release
June 2024 2024.2
  • Revised code examples in Optimize Inner Loop Throughput
  • Added "Filtering Nodes in Report Tables" to Review the FPGA Optimization Report
  • Revised Reduce Kernel Area and Latency (use_stall_enable_clusters).
  • Revised Declare the ap_float Data Type.
  • Revised Host Pipes RTL Interfaces.
  • Revised Partitioning Buffers Across Memory Channels of the Same Memory Type.
  • Added the no_offset property to FPGA Accessor Properties.
  • Revised The pipe Class and its Use.
  • Revised latency property description in The annotated_arg Template Class and Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class
  • Revised fpga_register description in Memory Attributes
  • Added Structs in RTL IP Core Interfaces
  • Revised Pipelined Kernels.
  • Revised ivdep Attribute.
  • Removed references to the --target sycl and --source sycl options of the fpga_crossgen and fpga_libtool commands. There options are no longer required and have been removed from the commands.
  • Replaced occurrences of <project_name>_di_inst.v with <project_name>_di_inst.sv.
  • Added Allow Wide Memory Initialization (-Xsallow-wide-device-globals).
  • Revised references to icpx -fscyl -fintelfpga commands to icpx -fintelfpga. The -fintelfpga option includes the -fsycl option, so specifying the -fsycl option is redunant.
  • Added Managing an FPGA Board.
  • Added Linking Your Host Application to the Khronos ICD Loader Library.
May 2024 2024.1
  • Fix broken links
March 2024 2024.1
  • Changed the title of this document to Intel® oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs.
  • Added The annotated_ptr Template Class.
  • Added Getting Started with Intel® oneAPI FPGA Development chapter. This chapter includes the following sections:
    • Installing the Intel® oneAPI FPGA Development Environment
    • FPGA Development for Intel® oneAPI Toolkits with Visual Studio* Code

      This section includes content that was previously provided in FPGA Development for Intel® oneAPI Toolkits with Visual Studio Code on Linux*.

      This section also includes new topics Enable Code Completion in Visual Studio Code and Debugging You Kernel In Visual Studio Code.

  • Revised Minimum Latency Flow.
  • Revised Balanced Throughput-Area Trade-Offs Flow.
  • Added Minimum Area Flow.
  • Revised information about encrypting your RTL IP core. Refer to Encrypting RTL IP Core for details.
  • Added Allow Wide Memory Initialization (-Xsallow-wide-mif) optimization target.
  • Added Integrating Your Kernel into DSP Builder for Intel FPGAs.
  • Removed references the following macros:
    • mmhost
    • register_map_mmhost
    • conduit_mmhost
    • streaming_interface
    • streaming_pipelined_interface
  • Deprecated the --emulation_model option of the fpga_crossgen. Use the --cpp_model option instead.
  • Renamed register_map_offsets.hpp and <kernel_name>_register_map.hpp files. Starting with oneAPI 2024.1, these files are register_map_offsets.h and <kernel_name>_register_map.h, respectively.
  • Revised FPGA BSPs and Boards.
  • Revised FPGA Compilation Flags
  • Changed the default compilation target when you do not specify the -Xstarget compiler option. If you do not specify the option, the compiler assumes -Xstarget=Agilex7. Previously, the default target was -Xstarget=intel_a10gx_pac:pac_a10.
  • Revised The device_global Extension (Beta).
  • Revised Declare the ac_fixed Data Type.
  • Moved System-level Profiling Using the Intercept Layer for OpenCL™ Applications to Optimizing Your Host Application section.
  • Rebrand Intel Agilex® 7 as Agilex™ 7
  • Rebrand Intel® Arria® 10 as Arria® 10
  • Rebrand Intel® Cyclone® 10 GX as Cyclone® 10 GX
  • Rebrand Intel® Cyclone® V as Cyclone® V
  • Rebrand Intel® Stratix® 10 as Stratix® 10
  • Rebrand Intel® Quartus® Prime as Quartus® Prime

Document Revision History for the Intel® oneAPI FPGA Handbook

This document was previous title Intel® oneAPI FPGA Handbook.

Date Release Version Changes
January 2024 2024.0
  • Revised Memory-Mapped (MM) Agent Kernel Invocation Interface.

    The topic previous listed bit 0 of the Start register as "reserved". Bit 0 is now correctly labeled "start".

November 2023 2024.0
  • Created Intel® oneAPI FPGA Handbook with content from FPGA Optimization Guide for Intel® oneAPI Toolkits and Intel® oneAPI Programming Guide.
  • Deprecated the following macros:
    • mmhost
    • register_map_mmhost
    • conduit_mmhost
    • streaming_interface
    • streaming_pipelined_interface
    These macros will be removed in a future release.
  • Updated Conversion Rules for the ap_float Data Type.
  • Added Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File.
  • Updated Agent IP Component Kernels.
  • Revised Host Pipes RTL Interfaces to indicate the restriction on simulation for host pipes with protocol_name::avalon_mm is lifted.
  • Updated The device_global Extension (Beta)
  • Revised Strategies for Inferring the Accumulator.
  • Renamed Maximum Throughput Without Area Optimization Heuristics Flow to Balanced Throughput-Area Trade-Offs Flow and revised the topic.
  • Revised ivdep Attribute
  • Added information about the annotated_arg class as follows:
    • Added Memory-Mapped Host Interfaces Using the annotated_arg Class
    • Added Avalon® Memory-Mapped Host Interfaces
    • Revised Memory-Mapped Host Interfaces
    • Revised Memory-Mapped Host Interfaces Using Unified Shared Memory
    • Revised Memory-Mapped Host Interfaces Using Accessors
  • Deprecated the [[intel::max_global_work_dim(0)]] kernel attribute in the following topics:
    • Omit Hardware that Generates and Dispatches Kernel IDs
    • FPGA Kernel Attributes
  • Renamed Agent IP Component Kernels to Avalon® Memory-Mapped (MM) Agent Kernel Invocation Interface and revised the topic.
  • Renamed Streaming IP Component Kernels to Ready/Valid Handshaking Kernel Invocation Interface and revised the topic.
  • Revised Pipelined Kernels

Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Most of the content in the Intel® oneAPI FPGA Handbook originally appeared in the FPGA Optimization Guide for Intel® oneAPI Toolkits.

Date Release Version Changes
July 2023 2023.2
  • Revised the note about SYCL streams support and mentioned about using sycl::ext::oneapi::experimental::printf for debugging kernels.
  • Updated all occurrences of -Xsno-interleaving=<global_memory_type> to -Xsno-interleaving=<global_memory_name>.
  • Revised the information in the following topics:
    • Optimization Targets
    • Minimum Latency Flow
    • Loop Analysis
    • Quartus (Static) Summary
    • Pipes
    • Simple Host-Device Streaming
    • Buffered Host-Device Streaming
  • Added the following new topics:
    • Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
    • Maximum Throughput Without Area Optimization Heuristics Flow
    • Create a 2xclock Interface (-Xsuse-2xclock)
    • Host Pipes
    • Host Pipe Declaration
    • Host Pipe API
    • Host Pipes RTL Interfaces
March 2023 2023.1
  • Added max_reinvocation_delay loop attribute.
  • Updated the limitations of AC data types in Advantages and Limitations of Arbitrary Precision Data Types.
  • Added another option to the -Xshyper-optimized-handshaking compiler flag in Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking).
  • Updated the values of supported data types and math operations in Control Hardware Implementation of the Supported Data Types and Math Operations.
  • Rebranded Intel® Agilex™ as Intel Agilex® 7.
  • Added device_globals extension.
  • Added Minimum Latency Flow.
  • Added Optimization Levels.
  • Revised the information in Perform Kernel Computations Using Local or Private Memory.
  • Reorganized all extensions under FPGA Extensions.
  • Added examples of declaring ac_complex variables in Declare the ac_complex Data Type.
December 2022 2023.0
  • Revised all references to #include <CL/...> as #include <sycl/...>.
  • Revised all references to using namespace cl::sycl; as using namespace sycl;.
  • Revised all references to dpcpp compiler driver to icpx -fsycl.
  • Added a note about avoiding adding the result of the convert_to function to another ap_float variable in Conversion Rules for ap_float.
  • Added a note about constant propagation optimization technique in Operations with Explicit Precision Controls.
  • Added additional about values supported by N for the [[intel::num_simd_work_items(N)]] attribute in Specify Number of SIMD Work-Items.
  • Revised Latency Controls topic to include a section on using latency controls with stall-free loop.
  • Added information about ihc::FPsingle and ihc::FPdouble to Declare the ap_float Data Type and Additional Data Types Provided by the ap_float.hpp Header File.
  • Added new sections on explicit conversion functions in Declare the ac_fixed Data Type and Declare the ac_int Data Type topics.
  • Removed deprecation notice for hls_float data type renamed to ap_float.
  • Added additional information about using the Intel® oneAPI FPGA Reports tool in Review the Optimization Report (report.html).
September 2022 2022.3
  • Added a note about setting the safelen parameter with 0 or 1 in ivdep Attribute.
  • Added a note about applying the ivdep attribute to an array in ivdep Attribute.
  • Minor update to example code in max_interleaving Attribute.
  • Updated all images and made moderate updates in all topics in the Analyze the FPGA Early Image section.
  • Made minor updates in Pipes topic.
  • Updated Latency Controls (Beta) topic completely.
  • Added a note about using the buffer_location<index> on BSPs with heterogeneous memory support in combination with read-only cache in Partitioning Buffers Across Different Memory Types (Heterogeneous Memory).
  • Revised the guidance in Timing Failures.
  • Made minor revisions in Zero-Copy Memory Access and Prepinning Memory topics.
  • Added the following new topics:
    • System of Tasks (task_sequence) Extension
    • Task Functions
    • task_sequence Use Cases
April 2022 2022.2
  • Changed the document title Intel® oneAPI DPC++ FPGA Optimization Guide to FPGA Optimization Guide for Intel® oneAPI Toolkits.
  • Replaced all general references to DPC++ with SYCL.
  • Added new loop functions to the existing list in FPGA Loop Directives.
  • Added a new limitation and removed some existing limitations in Advantages and Limitations of Arbitrary Precision Data Types.
  • Replaced all references to https://hlslibs.org/ with a reference to the documentation at https://github.com/hlslibs/ac_types/blob/v3.7/pdfdocs/ac_datatypes_ref.pdf.
  • Made a minor update to the description in The pipe Class and its Use.
  • Modified all occurrences of [[cl::reqd_work_group_size(Z, Y, X)]] to [[sycl::reqd_work_group_size(Z, Y, X)]]. [[cl::reqd_work_group_size(Z, Y, X)]] is now deprecated.
  • Added the following new topics:
    • Control Hardware Implementation of the Supported Data Types and Math Functions (-Xsdsp-mode=<option>)
    • Latency Controls
December 2021 2022.1
  • Added new attributes to the existing list in FPGA Loop Directives and FPGA Optimization Flags.
  • Added the following new topics:
    • Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>)
    • nofusion Attribute
    • Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>)
    • Renamed hls_float data type to ap_float. Added support for the header files <sycl/ext/intel/ac_types/ap_float.hpp> and <sycl/ext/intel/ac_types/ap_float_math.hpp>. In a future release, the header files <sycl/ext/intel/ac_types/hls_float.hpp> and <sycl/ext/intel/ac_types/hls_float_math.hpp> will be removed.
    • Updated few limitations in Advantages and Limitations of Arbitrary Precision Data Types.
September 2021 2021.4
  • Changed all occurrences of the namespace sycl::ONEAPI:: to sycl::ext::oneapi::.
  • Changed all occurrences of the namespace sycl::INTEL:: to sycl::ext::intel::.
  • Changed all occurrences of the header #include <CL/sycl/INTEL/...> to #include <sycl/ext/intel/...>.
  • Changed clang++ to dpcpp.
  • Changed all occurrences of [[intel::ii(n)]] to [[intel::initiation_interval(n)]].
  • Minor update about the types of FIFOs reported in the System Viewer.
  • Added a note about multi-process execution in the installed FPGAs in Multi-Threaded Host Application.
  • Added an additional value on to #pragma fp contract(fast/off).
  • Updated the code snippets in Specify Schedule FMAX Target for Kernels and Memory Attributes.
  • Modified the flag description for AC type in Variable-Precision Integer and Floating-Point Support.
  • Modified the list of limitations in Advantages and Limitations of Arbitrary Precision Data Types.
  • Added information about debugging in Declare the ac_int Data Type.
  • Added support for simulation flow.
  • Changed all occurrences of Mentor Graphics* to Siemens EDA* (formerly Mentor Graphics) .
  • Changed the noinit attribute to no_init.
  • Modified the description of [[intel::kernel_args_restrict]] attribute in Global Memory Accesses Optimization.
  • Replaced the flag -Xsffpcontract=<value> with -fp-model=<value> and updated its description in Reducing Floating-Point Rounding Operations.
  • Removed few limitations of shift register in Kernel Variable Accesses.
  • Added the following new topics:
    • Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>)
    • Reduce Kernel Area and Latency ([[intel::use_stall_enable_clusters]] attribute)
    • Timing Failures
July 2021 2021.3 Bug fixes.
June 2021 2021.3
  • Added more information about streaming data using I/O pipes and faking I/O pipes in I/O Pipes.
  • Added description about the local memory function in Kernel Memory.
  • Added a new section to describe the global memory bandwidth use calculation in Global Memory Accesses Optimization.
  • In System Viewer, added description about the global memory view, changed the Graph Viewer report name to System Viewer, updated all images and made minor updates in the remaining part of the topic.
  • Updated the description and image in Schedule Viewer.
  • Updated most of the code snippets to reflect the latest coding practices.
  • Made minor updates to the description of ivdep Attribute and loop_coalesce Attribute.
  • Added MLABs to the description in Perform Kernel Computations Using Local or Private Memory.
  • Modified the description in Strategies for Inferring the Accumulator to remove references to the -Xsfp-relaxed flag.
  • Updated the compilation options in Variable-Precision Integer and Floating-Point Support.
  • Updated the limitations in Advantages and Limitations of Arbitrary Precision Data Types.
  • Merged Ignoring Dependencies Between Accessor Arguments topic with Global Memory Accesses Optimization.
  • Updated the list of attributes in FPGA Kernel Attributes.
  • Added the following new topics:
    • Shannonization to Improve FMAX/II
    • Simple Host-device Streaming
    • Buffered Host-device Streaming
    • N-Way Buffering
    • Optimize Inner Loop Throughput
    • Improve Loop Performance by Caching On-Chip Memory
    • FPGA Local Memory Function
    • Pipelining Loops in Non-task Kernels (-Xsauto-pipeline)
    • Pipe and Atomic Fence
    • Reducing Floating-Point Rounding Operations (-Xsffp-contract=fast)
    • FPGA Accessor Properties
  • Removed the following topics because the respective flags are now deprecated:
    • Relax the Order of Floating-Point Operations (-Xsfp-relaxed)
    • Reduce Floating-Point Rounding Operations (-Xsfpc)
  • Removed Tree Balancing and Rounding Operations topic from Optimize Floating-point Operation.
March 2021 2021.2
  • Updated the topic Cluster the Datapath completely including the diagrams.
  • Updated the dependency graph in Mapping Source Code Instructions to Hardware.
  • Updated Hyper-Optimized Handshaking Data Flow diagram in Handshaking Between Clusters topic.
  • Made minor updates in Executing Independent Operations Simultaneously.
  • Updated the topic Pipelining completed including the diagrams.
  • Added a note about the enablement of fast math operations for floating point operations in Data Types and Operations.
  • Updated the topic Access HLD FPGA Reports in JSON Format to include details about the Bottlenecks viewer.
  • Made minor update to a note in Specify Number of SIMD Work-Items
  • Added the following new topics:
    • Floating Point Optimizations
    • Floating Point Pragmas
    • Specify Schedule FMAX Target for Kernels
    • Bottlenecks Viewer
    • Loop Bottlenecks
    • Variable-Precision Integer and Floating-Point Support
    • Advantages and Limitations of Arbitrary Precision Data Types
    • Declare and Use the AC Data Types
    • Declare the ac_int Data Type
    • Declare the ac_fixed Data Type
    • Declare the ac_complex Data Type
    • Declare the hls_float Data Type
    • Conversion Rules for hls_float
    • Operations with Explicit Precision Controls
    • Comparison Operators
    • Additional hls_float Functions
    • Additional Data Types Provided by hls_float.hpp
December 2020 2021.1 First major release.