Visible to Intel only — GUID: GUID-B55337C0-5A50-4595-9F2E-C9733FF8E494
Visible to Intel only — GUID: GUID-B55337C0-5A50-4595-9F2E-C9733FF8E494
Integrating Your RTL IP Core Into a System
To integrate your RTL IP core into a system with the Quartus® Prime software, you must be familiar with Quartus® Prime software, including Platform Designer.
The Intel® oneAPI DPC++/C++ Compiler generates a project directory (<project_name>.prj/) and a set of IP files per IP core. You can control this with the -fsycl-device-code-split=<off|per_source|per_kernel> option as follows:
- The default behavior (-fsycl-device-code-split not specified or -fsycl-device-code-split=off) combines all kernels in the source file into a single IP.
- Specifying -fsycl-device-code-split=per_kernel gives you a separate project directory (<project_name>.prj/), FPGA Optimization Report, set of IP files for each kernel.
The <project_name>.prj/ directory generated by the compiler contains all the files that you need to include your IP core in a Quartus® Prime project, including the following files:
top_<project_name>_di.ip
An IP file that you can add to your Quartus® Prime projects.
<project_name>_di_hw.tcl
A script that describes your IP core interfaces for Platform Designer.
<project_name>_di_inst.sv
An example of how to instantiate the IP into other Verilog modules.