HPS Address map for the HHP HPS system-domain Address: 0x0 Range: 0x100000000 Width: 32 FPGA Slaves Accessed Via HPS2FPGA AXI Bridge (hps2fpgaslaves) Address Map This address space is allocated for FPGA-configured slaves driven by the HPS-to-FPGA bridge master. The L2 cache filters determine how much of this window is visible to the MPU. For more information about the HPS-to-FPGA bridge, refer to the HPS-FPGA Bridges chapter of the Hard Processor System Technical Reference Manual. System Trace Macrocell (STM) Module Address Map This address space holds the registers used for System Trace Macrocell. For detailed information about the STM module and register descriptions, click here to access the documentation for the STM-101. Debug Access Port (DAP) Module Address Map This address space is allocated to the Debug Access Port (DAP). For detailed information about the use of this address space, click here to access the documentation for the DAP. FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge (lwfpgaslaves) Address Map This address space is allocated for FPGA-configured slaves driven by the lightweight HPS-to-FPGA bridge master. Address assignment within this space is user-defined. For more information about Lightweight HPS-to-FPGA bridges, refer to the HPS-FPGA Bridges chapter of the Hard Processor System Technical Reference Manual. LWHPS2FPGA AXI Bridge Module Address Map Registers in the LWHPS2FPGA AXI Bridge Module. HPS2FPGA AXI Bridge Module Address Map Registers in the HPS2FPGA AXI Bridge Module. FPGA2HPS AXI Bridge Module Address Map Registers in the FPGA2HPS AXI Bridge Module. EMAC Module Address Map Registers in the EMAC module. SDMMC Module Address Map Registers in the SD/MMC module QSPI Flash Controller Module Registers Address Map Registers in the QSPI Flash Controller module accessible via its APB slave FPGA Manager Module Address Map Registers in the FPGA Manager module accessible via its APB slave ACP ID Mapper Registers Address Map Registers in the ACP ID Mapper module GPIO Module Address Map Registers in the GPIO module L3 (NIC-301) GPV Registers Address Map Registers to control L3 interconnect settings NAND Controller Module Data (AXI Slave) Address Map This address space is allocated for indexed addressing by the NAND flash controller. QSPI Flash Module Data (AHB Slave) Address Map This address space is allocated for QSPI direct, indirect, and SPI legacy mode accesses. For more information, please refer to the Quad SPI Flash Controller chapter in the Hard Processor System Technical Reference Manual. USB OTG Controller Module Registers Address Map Registers in the USB OTG Controller Module. Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG Controller is operating in one mode, either Device or Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (GINTSTS.ModeMis). When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a power-on reset. The register address map is fixed and does not depend on the module configuration (for example, how many endpoints are implemented). Host and Device mode registers occupy different addresses. NAND Flash Controller Module Registers (AXI Slave) Address Map Registers in the NAND Flash Controller module accessible via its register AXI slave FPGA Manager Module Configuration Data Address Map Registers in the FPGA Manager module accessible via its AXI slave CAN Controller Module Address Map Registers in the CAN Controller module NOTE: These descriptions apply only to SoC devices that support the CAN module. UART Module Address Map Registers in the UART module I2C Module Address Map Registers in the I2C module Timer Module Address Map Registers in the timer module. The timer IP core supports multiple timers but it is configured for just one timer. The term Timer1 refers to this one timer in the IP core and not the module instance. SDRAM Controller Address Map Address map for the SDRAM Interface registers L4 Watchdog Module Address Map Registers in the L4 Watchdog module Clock Manager Module Address Map Registers in the Clock Manager module Reset Manager Module Address Map Registers in the Reset Manager module System Manager Module Address Map Registers in the System Manager module Non-Secure DMA Module Address Map This address space is allocated for non-secure DMA accesses. For detailed information about the use of this address space, click here to access the ARM documentation for the DMA-330. Secure DMA Module Address Map This address space is allocated for secure DMA accesses. For detailed information about the use of this address space, click here to access the documentation for the DMA-330. SPI Slave Module Address Map Registers in the SPI Slave module SPI Master Module Address Map Registers in the SPI Master module Scan Manager Module Registers Address Map Registers in the Scan Manager module. These registers are implemented by an JTAG-AP module from the DAP. Some register and field names have been changed to match the usage in the Scan Manager. If modified, the corresponding names from the documentation are provided. Only registers and fields that are relevant to the JTAG-AP use in the Scan Manager are listed. Boot ROM Address Map This address range is allocated for the boot ROM. MPU Address Map This address space is allocated to the MPU. For detailed information about the use of this address space, click here to access the documentation for the Cortex-A9 MPCore. MPU L2 Cache Controller (L2C-310) Module Address Map This address space is allocated to the MPU L2 cache controller. For detailed information about the use of this address space, click here to access the documentation for the L2C-310. On-chip RAM Address Map This is the address space allocated to the on-chip RAM. The on-chip RAM can be used by the HPS for storing data or user code.