SDRAM Controller Address Map
Address map for the SDRAM Interface registers
Base Address: 0xFFC20000
SDRAM Controller Module
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
ctrlcfg | 0x5000 | 32 | RW | 0x0 | Controller Configuration Register |
dramtiming1 | 0x5004 | 32 | RW | 0x0 | DRAM Timings 1 Register |
dramtiming2 | 0x5008 | 32 | RW | 0x0 | DRAM Timings 2 Register |
dramtiming3 | 0x500C | 32 | RW | 0x0 | DRAM Timings 3 Register |
dramtiming4 | 0x5010 | 32 | RW | 0x0 | DRAM Timings 4 Register |
lowpwrtiming | 0x5014 | 32 | RW | 0x0 | Lower Power Timing Register |
dramodt | 0x5018 | 32 | RW | 0x0 | ODT Control Register |
dramaddrw | 0x502C | 32 | RW | 0x0 | DRAM Address Widths Register |
dramifwidth | 0x5030 | 32 | RW | 0x0 | DRAM Interface Data Width Register |
dramsts | 0x5038 | 32 | RW | 0x0 | DRAM Status Register |
dramintr | 0x503C | 32 | RW | 0x0 | ECC Interrupt Register |
sbecount | 0x5040 | 32 | RW | 0x0 | ECC Single Bit Error Count Register |
dbecount | 0x5044 | 32 | RW | 0x0 | ECC Double Bit Error Count Register |
erraddr | 0x5048 | 32 | RW | 0x0 | ECC Error Address Register |
dropcount | 0x504C | 32 | RW | 0x0 | ECC Auto-correction Dropped Count Register |
dropaddr | 0x5050 | 32 | RW | 0x0 | ECC Auto-correction Dropped Address Register |
lowpwreq | 0x5054 | 32 | RW | 0x0 | Low Power Control Register |
lowpwrack | 0x5058 | 32 | RW | 0x0 | Low Power Acknowledge Register |
staticcfg | 0x505C | 32 | RW | 0x0 | Static Configuration Register |
ctrlwidth | 0x5060 | 32 | RW | 0x0 | Memory Controller Width Register |
portcfg | 0x507C | 32 | RW | 0x0 | Port Configuration Register |
fpgaportrst | 0x5080 | 32 | RW | 0x0 | FPGA Ports Reset Control Register |
protportdefault | 0x508C | 32 | RW | 0x0 | Memory Protection Port Default Register |
protruleaddr | 0x5090 | 32 | RW | 0x0 | Memory Protection Address Register |
protruleid | 0x5094 | 32 | RW | 0x0 | Memory Protection ID Register |
protruledata | 0x5098 | 32 | RW | 0x0 | Memory Protection Rule Data Register |
protrulerdwr | 0x509C | 32 | RW | 0x0 | Memory Protection Rule Read-Write Register |
mppriority | 0x50AC | 32 | RW | 0x0 | Scheduler priority Register |
remappriority | 0x50E0 | 32 | RW | 0x0 | Controller Command Pool Priority Remap Register |
Port Sum of Weight Register
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
mpweight_0_4 | 0x50B0 | 32 | RW | 0x0 | Port Sum of Weight Register[1/4] |
mpweight_1_4 | 0x50B4 | 32 | RW | 0x0 | Port Sum of Weight Register[2/4] |
mpweight_2_4 | 0x50B8 | 32 | RW | 0x0 | Port Sum of Weight Register[3/4] |
mpweight_3_4 | 0x50BC | 32 | RW | 0x0 | Port Sum of Weight Register[4/4] |