SPI Master Module Address Map

Registers in the SPI Master module
Module Instance Base Address
spim0 0xFFF00000
spim1 0xFFF01000

SPI Master Module

Register Offset Width Access Reset Value Description
ctrlr0 0x0 32 RW 0x7 Control Register 0
ctrlr1 0x4 32 RW 0x0 Control Register 1
spienr 0x8 32 RW 0x0 Enable Register
mwcr 0xC 32 RW 0x0 Microwire Control Register
ser 0x10 32 RW 0x0 Slave Enable Register
baudr 0x14 32 RW 0x0 Baud Rate Select Register
txftlr 0x18 32 RW 0x0 Transmit FIFO Threshold Level Register
rxftlr 0x1C 32 RW 0x0 Receive FIFO Threshold Level Register
txflr 0x20 32 RO 0x0 Transmit FIFO Level Register
rxflr 0x24 32 RO 0x0 Receive FIFO Level Register
sr 0x28 32 RO 0x6 Status Register
imr 0x2C 32 RW 0x3F Interrupt Mask Register
isr 0x30 32 RO 0x0 Interrupt Status Register
risr 0x34 32 RO 0x0 Raw Interrupt Status Register
txoicr 0x38 32 RO 0x0 Transmit FIFO Overflow Interrupt Clear Register
rxoicr 0x3C 32 RO 0x0 Receive FIFO Overflow Interrupt Clear Register
rxuicr 0x40 32 RO 0x0 Receive FIFO Underflow Interrupt Clear Register
icr 0x48 32 RO 0x0 Interrupt Clear Register
dmacr 0x4C 32 RW 0x0 DMA Control Register
dmatdlr 0x50 32 RW 0x0 DMA Transmit Data Level Register
dmardlr 0x54 32 RW 0x0 DMA Receive Data Level Register
idr 0x58 32 RO 0x5510000 Identification Register
spi_version_id 0x5C 32 RW 0x3332302A Component Version Register
dr 0x60 32 RW 0x0 Data Register
rx_sample_dly 0xF0 32 RW 0x0 RX Sample Delay Register