FPGA Manager Module Address Map

Registers in the FPGA Manager module accessible via its APB slave

Base Address: 0xFF706000

FPGA Manager Module

Register Offset Width Access Reset Value Description
stat 0x0 32 RW 0x45 Status Register
ctrl 0x4 32 RW 0x200 Control Register
dclkcnt 0x8 32 RW 0x0 DCLK Count Register
dclkstat 0xC 32 RW 0x0 DCLK Status Register
gpo 0x10 32 RW 0x0 General-Purpose Output Register
gpi 0x14 32 RO 0x0 General-Purpose Input Register
misci 0x18 32 RO 0x0 Miscellaneous Input Register

Configuration Monitor (MON) Registers

Register Offset Width Access Reset Value Description
gpio_inten 0x830 32 RW 0x0 Interrupt Enable Register
gpio_intmask 0x834 32 RW 0x0 Interrupt Mask Register
gpio_inttype_level 0x838 32 RW 0x0 Interrupt Level Register
gpio_int_polarity 0x83C 32 RW 0x0 Interrupt Polarity Register
gpio_intstatus 0x840 32 RO 0x0 Interrupt Status Register
gpio_raw_intstatus 0x844 32 RO 0x0 Raw Interrupt Status Register
gpio_porta_eoi 0x84C 32 WO 0x0 Clear Interrupt Register
gpio_ext_porta 0x850 32 RO 0x0 External Port A Register
gpio_ls_sync 0x860 32 RW 0x0 Synchronization Level Register
gpio_ver_id_code 0x86C 32 RO 0x3230382A GPIO Version Register
gpio_config_reg2 0x870 32 RO 0x39CEB Configuration Register 2
gpio_config_reg1 0x874 32 RO 0x1F50F2 Configuration Register 1