mppriority

This register is used to configure the DRAM burst operation scheduling.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC250AC

Offset: 0x50AC

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

userpriority

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

userpriority

RW 0x0

mppriority Fields

Bit Name Description Access Reset
29:0 userpriority

User Priority: This field sets the absolute user priority of each port, which is represented as a 3-bit value. 0x0 is the lowest priority and 0x7 is the highest priority. Port 0 is configured by programming userpriority[2:0], port 1 is configured by programming userpriority[5:3], port 2 is configured by programming userpriority[8:6], and so on.

RW 0x0