dramaddrw

This register configures the width of the various address fields of the DRAM. The values specified in this register must match the memory devices being used.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC2502C`

Offset: 0x502C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`csbits` `RW 0x0`			`bankbits` `RW 0x0`			`rowbits` `RW 0x0`					`colbits` `RW 0x0`

dramaddrw Fields

Bit	Name	Description	Access	Reset
15:13	`csbits`	This field defines the number of chip select address bits. Set this field to 0x0 for single chip select and to 0x1 for two chip selects. When this field is set to 0x1, you may use rank interleaved mode by programming the ctrlcfg.addrorder field to 0x2. If you are using a single rank memory interface (csbits=0x0), you may not enable the rank interleaved mode (ctrlcfg.addrorder must be set less than 0x2). When this field is set to 0x1 to enable dual ranks, the chip select (cs) bit of the incoming address is used to determine which chip select is active. When the chip select bit of the incoming address is 0, chip select 0 becomes active. When the chip select bit of the incoming address is 1, chip select 1 becomes active.	`RW`	`0x0`
12:10	`bankbits`	The number of bank address bits for the memory devices in your memory interface.	`RW`	`0x0`
9:5	`rowbits`	The number of row address bits for the memory devices in your memory interface.	`RW`	`0x0`
4:0	`colbits`	The number of column address bits for the memory devices in your memory interface.	`RW`	`0x0`