dramsts

This register provides the status of the calibration and ECC logic.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC25038`

Offset: 0x5038

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`											`corrdrop` `RW 0x0`	`dbeerr` `RW 0x0`	`sbeerr` `RW 0x0`	`calfail` `RW 0x0`	`calsuccess` `RW 0x0`

dramsts Fields

Bit	Name	Description	Access	Reset
4	`corrdrop`	This bit is set to 1 when any auto-corrections have been dropped.	`RW`	`0x0`
3	`dbeerr`	This bit is set to 1 when any ECC double bit errors are detected.	`RW`	`0x0`
2	`sbeerr`	This bit is set to 1 when any ECC single bit errors are detected.	`RW`	`0x0`
1	`calfail`	This bit is set to 1 when the PHY is unable to calibrate.	`RW`	`0x0`
0	`calsuccess`	This bit will be set to 1 if the PHY was able to successfully calibrate.	`RW`	`0x0`