dramtiming1

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC25004

Offset: 0x5004

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

trfc

RW 0x0

tfaw

RW 0x0

trrd

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

trrd

RW 0x0

tcl

RW 0x0

tal

RW 0x0

tcwl

RW 0x0

dramtiming1 Fields

Bit Name Description Access Reset
31:24 trfc

The refresh cycle timing parameter.

 RW 0x0
23:18 tfaw

The four-activate window timing parameter.

 RW 0x0
17:14 trrd

The activate to activate, different banks timing parameter.

 RW 0x0
13:9 tcl

Memory read latency.

 RW 0x0
8:4 tal

Memory additive latency.

 RW 0x0
3:0 tcwl

Memory write latency.

 RW 0x0