SDRAM Controller Module Register Descriptions Address map for the SDRAM controller and multi-port front-end. All registers in this group reset to zero. Offset: 0x5000 ctrlcfg The Controller Configuration Register determines the behavior of the controller. dramtiming1 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. dramtiming2 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. dramtiming3 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. dramtiming4 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. lowpwrtiming This register controls the behavior of the low power logic in the controller. dramodt This register controls which ODT pin asserts with chip select 0 (CS0) assertion and which ODT pin asserts with chip select 1 (CS1) assertion. dramaddrw This register configures the width of the various address fields of the DRAM. The values specified in this register must match the memory devices being used. dramifwidth This register controls the interface width of the SDRAM controller. dramsts This register provides the status of the calibration and ECC logic. dramintr This register can enable, disable and clear the SDRAM error interrupts. sbecount This register tracks the single-bit error count. dbecount This register tracks the double-bit error count. erraddr This register holds the address of the most recent ECC error. dropcount This register holds the address of the most recent ECC error. dropaddr This register holds the last dropped address. lowpwreq This register instructs the controller to put the DRAM into a power down state. Note that some commands are only valid for certain memory types. lowpwrack This register gives the status of the power down commands requested by the Low Power Control register. staticcfg This register controls configuration values which cannot be updated during active transfers. First configure the membl and eccn fields and then re-write these fields while setting the applycfg bit. The applycfg bit is write only. ctrlwidth This register controls the width of the physical DRAM interface. portcfg Each bit of the autopchen field maps to one of the control ports. If a port executes mostly sequential memory accesses, the corresponding autopchen bit should be 0. If the port has highly random accesses, then its autopchen bit should be set to 1. fpgaportrst This register implements functionality to allow the CPU to control when the MPFE will enable the ports to the FPGA fabric. protportdefault This register controls the default protection assignment for a port. Ports which have explicit rules which define regions which are illegal to access should set the bits to pass by default. Ports which have explicit rules which define legal areas should set the bit to force all transactions to fail. Leaving this register to all zeros should be used for systems which do not desire any protection from the memory controller. protruleaddr This register is used to control the memory protection for port 0 transactions. Address ranges can either be used to allow access to memory regions or disallow access to memory regions. If TrustZone® is being used, access can be enabled for protected transactions or disabled for unprotected transactions. The default state of this register is to allow all access. Address values used for protection are only physical addresses. protruleid This register configures the AxID for a given protection rule. protruledata This register configures the protection memory characteristics of each protection rule. protrulerdwr This register is used to perform read and write operations to the internal protection table. mppriority This register is used to configure the DRAM burst operation scheduling. remappriority This register applies another level of port priority after a transaction is placed in the single port queue. Port Sum of Weight Register Register Descriptions This register is used to configure the DRAM burst operation scheduling.