lowpwrack
This register gives the status of the power down commands requested by the Low Power Control register.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sdr | 0xFFC20000 | 0xFFC25058 |
Offset: 0x5058
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
selfrfshack RW 0x0 |
deeppwrdnack RW 0x0 |
|||||||||||||
lowpwrack Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 1 | selfrfshack | This bit is a one to indicate that the controller is in a self-refresh state. |
RW | 0x0 |
| 0 | deeppwrdnack | This bit is set to a one after a deep power down has been executed |
RW | 0x0 |