dramtiming4

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC25010

Offset: 0x5010

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

minpwrsavecycles

RW 0x0

pwrdownexit

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

pwrdownexit

RW 0x0

selfrfshexit

RW 0x0

dramtiming4 Fields

Bit Name Description Access Reset
23:20 minpwrsavecycles

The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR.

 RW 0x0
19:10 pwrdownexit

The power down exit cycles, tXPDLL.

 RW 0x0
9:0 selfrfshexit

The self refresh exit cycles, tXS.

 RW 0x0