ctrlcfg

The Controller Configuration Register determines the behavior of the controller.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC25000

Offset: 0x5000

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

bursttermen

RW 0x0

burstintren

RW 0x0

nodmpins

RW 0x0

dqstrken

RW 0x0

starvelimit

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reorderen

RW 0x0

gendbe

RW 0x0

gensbe

RW 0x0

cfg_enable_ecc_code_overwrites

RW 0x0

ecccorren

RW 0x0

eccen

RW 0x0

addrorder

RW 0x0

membl

RW 0x0

memtype

RW 0x0

ctrlcfg Fields

Bit Name Description Access Reset
25 bursttermen

Set to a one to enable the controller to issue burst terminate commands. This must only be set when the DRAM memory type is LPDDR2.

 RW 0x0
24 burstintren

Set to a one to enable the controller to issue burst interrupt commands. This must only be set when the DRAM memory type is LPDDR2.

 RW 0x0
23 nodmpins

Set to a one to enable DRAM operation if no DM pins are connected.

 RW 0x0
22 dqstrken

Enables DQS tracking in the PHY.

 RW 0x0
21:16 starvelimit

Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller.

 RW 0x0
15 reorderen

This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth. It should generally be set to a one.

 RW 0x0
14 gendbe

Enable the deliberate insertion of double bit errors in data written to memory. This should only be used for testing purposes.

 RW 0x0
13 gensbe

Enable the deliberate insertion of single bit errors in data written to memory. This should only be used for testing purposes.

 RW 0x0
12 cfg_enable_ecc_code_overwrites

Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable ECC error is seen and cause a new read/modify/write to be scheduled for that location to clear the ECC error.

 RW 0x0
11 ecccorren

Enable auto correction of the read data returned when single bit error is detected.

 RW 0x0
10 eccen

Enable the generation and checking of ECC. This bit must only be set if the memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, you must clear the useeccasdata field in the staticcfg register.

 RW 0x0
9:8 addrorder

This bit field selects the order for address interleaving. Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering.

Value Description Address Interleaving
0x0 chip, row, bank, column Bank interleaved with no rank (chip select) interleaving
0x1 chip, bank, row, column No interleaving
0x2 row, chip, bank, column Bank interleaved with rank (chip select) interleaving
0x3 reserved N/A
recommends programming addrorder to 0x0 or 0x2.
 RW 0x0
7:3 membl

Configures burst length as a static decimal value. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this should be programmed with 8 (binary "01000"), for DDR2 it can be either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program the membl field in the staticcfg register.

 RW 0x0
2:0 memtype
This bit field selects the memory type. This field can be programmed with the following binary values:
Value Description
0x0 Reserved
0x1 Memory type is DDR2 SDRAM
0x2 Memory type is DDR3 SDRAM
0x3 reserved
0x4 Memory type is LPDDR2 SDRAM
0x5-0x7 Reserved
RW 0x0