sdmmc Summary

Base Address: 0xFF808000

Register

Address Offset

Bit Fields
i_sdmmc_sdmmc

ctrl

0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

use_internal_dmac

RW 0x0

enable_od_pullup

RW 0x0

card_voltage_b

RW 0x0

card_voltage_a

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ceata_device_interrupt_status

RW 0x0

send_auto_stop_ccsd

RW 0x0

send_ccsd

RW 0x0

abort_read_data

RW 0x0

send_irq_response

RW 0x0

read_wait

RW 0x0

dma_enable

RW 0x0

int_enable

RW 0x0

Reserved

dma_reset

RW 0x0

fifo_reset

RW 0x0

controller_reset

RW 0x0

pwren

0x4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

power_enable

RW 0x0

clkdiv

0x8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

clk_divider3

RO 0x0

clk_divider2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

clk_divider1

RO 0x0

clk_divider0

RW 0x0

clksrc

0xC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

clk_source

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

clk_source

RO 0x0

clkena

0x10

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cclk_low_power

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cclk_enable

RW 0x0

tmout

0x14

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

data_timeout

RW 0xFFFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

data_timeout

RW 0xFFFFFF

response_timeout

RW 0x40

ctype

0x18

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

card_width1

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

card_width2

RW 0x0

blksiz

0x1C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

block_size

RW 0x200

bytcnt

0x20

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

byte_count

RW 0x200

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

byte_count

RW 0x200

intmask

0x24

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

sdio_int_mask

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RW 0x0

acd

RW 0x0

sbe

RW 0x0

hle

RW 0x0

frun

RW 0x0

hto

RW 0x0

drt

RW 0x0

rto

RW 0x0

dcrc

RW 0x0

rcrc

RW 0x0

rxdr

RW 0x0

txdr

RW 0x0

dto

RW 0x0

cmd

RW 0x0

re

RW 0x0

cd

RW 0x0

cmdarg

0x28

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cmd_arg

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cmd_arg

RW 0x0

cmd

0x2C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

start_cmd

RW 0x0

Reserved

use_hold_reg

RW 0x1

volt_switch

RW 0x0

boot_mode

RW 0x0

disable_boot

RW 0x0

expect_boot_ack

RW 0x0

enable_boot

RW 0x0

ccs_expected

RW 0x0

read_ceata_device

RW 0x0

update_clock_registers_only

RW 0x0

card_number

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

send_initialization

RW 0x0

stop_abort_cmd

RW 0x0

wait_prvdata_complete

RW 0x0

send_auto_stop

RW 0x0

transfer_mode

RW 0x0

read_write

RW 0x0

data_expected

RW 0x0

check_response_crc

RW 0x0

response_length

RW 0x0

response_expect

RW 0x0

cmd_index

RW 0x0

resp0

0x30

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

response0

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response0

RO 0x0

resp1

0x34

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

response1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response1

RO 0x0

resp2

0x38

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

response2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response2

RO 0x0

resp3

0x3C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

response3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response3

RO 0x0

mintsts

0x40

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

sdio_interrupt

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RO 0x0

acd

RO 0x0

strerr

RO 0x0

hlwerr

RO 0x0

fifoovunerr

RO 0x0

dshto

RO 0x0

datardto

RO 0x0

respto

RO 0x0

datacrcerr

RO 0x0

respcrcerr

RO 0x0

rxfifodr

RO 0x0

dttxfifodr

RO 0x0

dt

RO 0x0

cmd_done

RO 0x0

resp

RO 0x0

cd

RO 0x0

rintsts

0x44

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

sdio_interrupt

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RW 0x0

acd

RW 0x0

sbe

RW 0x0

hle

RW 0x0

frun

RW 0x0

hto

RW 0x0

bds

RW 0x0

bar

RW 0x0

dcrc

RW 0x0

rcrc

RW 0x0

rxdr

RW 0x0

txdr

RW 0x0

dto

RW 0x0

cmd

RW 0x0

re

RW 0x0

cd

RW 0x0

status

0x48

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dma_req

RO 0x0

dma_ack

RO 0x0

fifo_count

RO 0x0

response_index

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response_index

RO 0x0

data_state_mc_busy

RO 0x0

data_busy

RO 0x0

data_3_status

RO 0x1

command_fsm_states

RO 0x0

fifo_full

RO 0x0

fifo_empty

RO 0x1

fifo_tx_watermark

RO 0x1

fifo_rx_watermark

RO 0x0

fifoth

0x4C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

dw_dma_multiple_transaction_size

RW 0x0

rx_wmark

RW 0x3FF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tx_wmark

RW 0x0

cdetect

0x50

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

card_detect_n

RO 0x1

wrtprt

0x54

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

write_protect

RO 0x1

tcbcnt

0x5C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

trans_card_byte_count

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

trans_card_byte_count

RO 0x0

tbbcnt

0x60

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

trans_fifo_byte_count

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

trans_fifo_byte_count

RO 0x0

debnce

0x64

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

debounce_count

RW 0xFFFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

debounce_count

RW 0xFFFFFF

usrid

0x68

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

usr_id

RW 0x7967797

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

usr_id

RW 0x7967797

verid

0x6C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ver_id

RO 0x5342270A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ver_id

RO 0x5342270A

hcon

0x70

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ac

RO 0x0

aro

RO 0x0

ncd

RO 0x0

scfp

RO 0x1

ihr

RO 0x1

rios

RO 0x0

dmadatawidth

RO 0x1

dmaintf

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

haddrwidth

RO 0xC

hdatawidth

RO 0x1

hbus

RO 0x0

nc

RO 0x0

ct

RO 0x1

uhs_reg

0x74

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ddr_reg

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

volt_reg

RW 0x0

rst_n

0x78

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

card_reset

RW 0x1

bmod

0x80

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

pbl

RO 0x0

de

RW 0x0

dsl

RW 0x0

fb

RW 0x0

swr

RW 0x0

pldmnd

0x84

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

pd

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

pd

WO 0x0

dbaddr

0x88

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

sdl

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

sdl

RW 0x0

idsts

0x8C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

fsm

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fsm

RO 0x0

eb

RO 0x0

ais

RW 0x0

nis

RW 0x0

Reserved

ces

RW 0x0

du

RW 0x0

Reserved

fbe

RW 0x0

ri

RW 0x0

ti

RW 0x0

idinten

0x90

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ai

RW 0x0

ni

RW 0x0

Reserved

ces

RW 0x0

du

RW 0x0

Reserved

fbe

RW 0x0

ri

RW 0x0

ti

RW 0x0

dscaddr

0x94

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

hda

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

hda

RO 0x0

bufaddr

0x98

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

hba

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

hba

RO 0x0

cardthrctl

0x100

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cardrdthreshold

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

busy_clr_int_en

RW 0x0

cardrdthren

RW 0x0

back_end_power_r

0x104

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

back_end_power

RW 0x0

data

0x200

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

value

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

value

RW 0x0

gpio

0x58

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

gpo

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

gpo

RW 0x0

gpi

RO 0x0

uhs_reg_ext

0x108

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ext_clk_mux_ctrl

RW 0x0

clk_drv_phase_ctrl

RW 0x0

clk_smpl_phase_ctrl

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mmc_volt_reg

RW 0x0

emmc_ddr_reg

0x10C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

half_start_bit

RW 0x0

enable_shift

0x110

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

enable_shift_card

RW 0x0