clkdiv
Clock Divider Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sdmmc_sdmmc | 0xFF808000 | 0xFF808008 |
Offset: 0x8
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
clk_divider3 RO 0x0 |
clk_divider2 RO 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
clk_divider1 RO 0x0 |
clk_divider0 RW 0x0 |
||||||||||||||
clkdiv Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:24 | clk_divider3 | Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. |
RO | 0x0 |
| 23:16 | clk_divider2 | Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. |
RO | 0x0 |
| 15:8 | clk_divider1 | Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported |
RO | 0x0 |
| 7:0 | clk_divider0 | Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. |
RW | 0x0 |