ctrl
Control register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sdmmc_sdmmc | 0xFF808000 | 0xFF808000 |
Offset: 0x0
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
use_internal_dmac RW 0x0 |
enable_od_pullup RW 0x0 |
card_voltage_b RW 0x0 |
card_voltage_a RW 0x0 |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
ceata_device_interrupt_status RW 0x0 |
send_auto_stop_ccsd RW 0x0 |
send_ccsd RW 0x0 |
abort_read_data RW 0x0 |
send_irq_response RW 0x0 |
read_wait RW 0x0 |
dma_enable RW 0x0 |
int_enable RW 0x0 |
Reserved |
dma_reset RW 0x0 |
fifo_reset RW 0x0 |
controller_reset RW 0x0 |
|||
ctrl Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 25 | use_internal_dmac | Present only for the Internal DMAC configuration; else, it is reserved.
0-The host performs data transfers through the slave interface
1-Internal DMAC used for data transfer
|
RW | 0x0 | ||||||
| 24 | enable_od_pullup | External open-drain pullup
0-Disable
1-Enable
Inverted value of this bit is output to ccmd_od_pullup_en_n port.
When bit is set, command output always driven in open-drive mode; that is, DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1.
|
RW | 0x0 | ||||||
| 23:20 | card_voltage_b | Card regulator-B voltage setting; output to card_volt_b port. Optional feature; ports can be used as general-purpose outputs |
RW | 0x0 | ||||||
| 19:16 | card_voltage_a | Card regulator-A voltage setting; output to card_volt_a port. Optional feature; ports can be used as general-purpose outputs |
RW | 0x0 | ||||||
| 11 | ceata_device_interrupt_status | 0-Interrupts not enabled in CE-ATA device
1-Interrupts are enabled in CE-ATA device
|
RW | 0x0 | ||||||
| 10 | send_auto_stop_ccsd | 0-Clear bit if DWC_mobile_storage does not reset the bit
1-Send internally generated STOP after sending CCSD to
CE-ATA device
|
RW | 0x0 | ||||||
| 9 | send_ccsd | 0-Clear this bit if DWC_mobile_storage does not reset the bit 1-Send Command Completion Signal Disable (CCSD) to CE-ATA device
|
RW | 0x0 | ||||||
| 8 | abort_read_data | 0-No change
1-After suspend command is issued during read-transfer, software
polls card to find when suspend happened. Once suspend occurs,software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data statemachine resets to idle.
Used in SDIO card suspend sequence.
|
RW | 0x0 | ||||||
| 7 | send_irq_response | 0-No Change in this
1-Send auto IRQ response
Bit automatically clears once response is sent.
To wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits for interrupt response from MMC card(s). In meantime, if host wants DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at which time DWC_mobile_storage command state-machine sends CMD40 response on bus and returns to idle state.
|
RW | 0x0 | ||||||
| 6 | read_wait | 0-Clear read wait
1-Assert read wait
For sending read-wait to SDIO cards.
|
RW | 0x0 | ||||||
| 5 | dma_enable | 0-Disable DMA transfer mode
1-Enable DMA transfer mode
Valid only if DWC_mobile_storage configured for External DMA interface.
|
RW | 0x0 | ||||||
| 4 | int_enable | Global interrupt enable/disable bit:
0-Disable interrupts
1-Enable interrupts
The int port is 1 only when this bit is 1 and one or more unmasked
interrupts are set.
|
RW | 0x0 | ||||||
| 2 | dma_reset | 0-No change
1-Reset internal DMA interface control logic
To reset DMA interface, firmware should set bit to 1. This bit is
auto-cleared after two AHB clocks.
|
RW | 0x0 | ||||||
| 1 | fifo_reset | 0-No change
1-Reset to data FIFO To reset FIFO pointers
To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.
|
RW | 0x0 | ||||||
| 0 | controller_reset | 0-No change
1-Reset DWC_mobile_storage controller
To reset controller, firmware should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles.
This resets:
* BIU/CIU interface
* CIU and state machines
* abort_read_data, send_irq_response, and read_wait bits of Control register
* start_cmd bit of Command register
Does not affect any registers or DMA interface, or FIFO or host
interrupts
|
RW | 0x0 |