uhs_reg_ext

         UHS Register Extention
Module Instance Base Address Register Address
i_sdmmc_sdmmc 0xFF808000 0xFF808108

Offset: 0x108

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ext_clk_mux_ctrl

RW 0x0

clk_drv_phase_ctrl

RW 0x0

clk_smpl_phase_ctrl

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mmc_volt_reg

RW 0x0

uhs_reg_ext Fields

Bit Name Description Access Reset
31:30 ext_clk_mux_ctrl 
Input clock control for cclk_in. The MUX controlled by these bits exists outside DWC_mobile_storage IP.
 RW 0x0
29:23 clk_drv_phase_ctrl 
Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively, use only LSBs.
 RW 0x0
22:16 clk_smpl_phase_ctrl 
Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively, use only LSBs.
 RW 0x0
15:0 mmc_volt_reg 
Support for 1.2V. MMC_VOLT_REG bits; must be read in combination 
with UHS_VOLT_REG to decode output selected voltage.
The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination selected for the I/O voltage logic.
Host controllers that support only SD standard or standard versions before eMMC4.41 do not program MMC_VOLT_REG. 
Only host controllers that support all three versions3.3,1.8,1.2 Vcan program MMC_VOLT_REG and connect biu_volt_reg_1_2.
 RW 0x0