pldmnd

         Poll Demand Register

Module Instance	Base Address	Register Address
`i_sdmmc_sdmmc`	`0xFF808000`	`0xFF808084`

Offset: 0x84

Access: WO

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`pd` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`pd` `WO 0x0`

pldmnd Fields

Bit	Name	Description	Access	Reset
31:0	`pd`	Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only.	`WO`	`0x0`

Bit

Name

Description

Access

Reset

31:0

pd

Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal 
descriptor fetch operation. This is a write only register.
PD bit is write-only.

WO

0x0