hmc_adp_csr_ocp_slv_block Address Map

Block
Module Instance Base Address End Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF80114FF
Register Offset Width Access Reset Value Description
IP_REV_ID 0x0 32 RO 0x00000000 
IP_REV_ID
DDRIOCTRL 0x08 32 RW 0x00000000 
DDR IO Control Register
DDRCALSTAT 0x00C 32 RO 0x00000000 
DDR Calibration Status Register
MPR_0BEAT1 0x010 32 RO 0x00000000 
MPR register [31:0] for first beat
MPR_1BEAT1 0x014 32 RO 0x00000000 
MPR register [63:32] for first beat
MPR_2BEAT1 0x018 32 RO 0x00000000 
MPR register [95:64] for first beat
MPR_3BEAT1 0x01C 32 RO 0x00000000 
MPR register [127:96] for first beat
MPR_4BEAT1 0x020 32 RO 0x00000000 
MPR register [159:128] for first beat
MPR_5BEAT1 0x024 32 RO 0x00000000 
MPR register [191:160] for first beat
MPR_6BEAT1 0x028 32 RO 0x00000000 
MPR register [223:192] for first beat
MPR_7BEAT1 0x02C 32 RO 0x00000000 
MPR register [255:224] for first beat
MPR_8BEAT1 0x030 32 RO 0x00000000 
MPR register [287:256] for first beat
MPR_0BEAT2 0x034 32 RO 0x00000000 
MPR register [31:0] for second beat
MPR_1BEAT2 0x038 32 RO 0x00000000 
MPR register [63:32] for second beat
MPR_2BEAT2 0x03C 32 RO 0x00000000 
MPR register [95:64] for second beat
MPR_3BEAT2 0x040 32 RO 0x00000000 
MPR register [127:96] for second beat
MPR_4BEAT2 0x044 32 RO 0x00000000 
MPR register [159:128] for second beat
MPR_5BEAT2 0x048 32 RO 0x00000000 
MPR register [191:160] for second beat
MPR_6BEAT2 0x04C 32 RO 0x00000000 
MPR register [223:192] for second beat
MPR_7BEAT2 0x050 32 RO 0x00000000 
MPR register [255:224] for second beat
MPR_8BEAT2 0x054 32 RO 0x00000000 
MPR register [287:256] for second beat
AUTO_PRECHARGE 0x60 32 RW 0x00000000 
auto-precharge bit
MPFE_HMCA_SPARE1 0xE0 32 RW 0x00000000 
spare configuration register
ECCCTRL1 0x100 32 RW 0x00000000 
ECC control 1.
This bit is used to set the initialize the memory and ecc to a known value
ECCCTRL2 0x104 32 RW 0x00000000 
ECC control 2.
This bit is used to set the initialize the memory and ecc to a known value
ERRINTEN 0x110 32 RW 0x00000000 
Error Interrupt enable
ERRINTENS 0x114 32 RW 0x00000000 
Error Interrupt set
ERRINTENR 0x118 32 RW 0x00000000 
Error Interrupt reset.
INTMODE 0x11C 32 RW 0x00000000 
Interrupt mode
INTSTAT 0x120 32 RW 0x00000000 
Interrupt status
DIAGINTTEST 0x124 32 RW 0x00000000 
Enable diagnostic errors
MODSTAT 0x128 32 RW 0x00000000 
Counter feature status flag
DERRADDRA 0x12C 32 RO 0x00000000 
Double-bit error address
SERRADDRA 0x130 32 RO 0x00000000 
Single-bit error address
AUTOWB_CORRADDR 0x138 32 RO 0x00000000 
This register shows the address of the current autoWB correction SBE.
SERRCNTREG 0x13C 32 RW 0x00000000 
Maximum counter value for single-bit error interrupt
AUTOWB_DROP_CNTREG 0x140 32 RW 0x00000001 
Maximum counter value for AUTOWB correction interrupt
ECC_REG2AWRECCDATABUS 0x144 32 RW 0x00000000 
ECC [Lower] from register associated to data which will be written to the RAM
MPFE_HMCA_SPARE2 0x148 32 RO 0x00000000 
spare status register
ECC_REG2ARDECCDATABUS 0x14C 32 RW 0x00000000 
ECC [Lower] from register associated to RD data which will be written to hmc ecc
ECC_DIAGON 0x150 32 RW 0x00000000 
Enable diagnostics access
ECC_DECSTAT 0x154 32 RW 0x00000000 
Diagnostic decoder status
ECC_ERRGENADDR_0 0x160 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_1 0x164 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_2 0x168 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_3 0x16C 32 RO 0x00000000 
Error address register
ECC_REG2ARDDATABUS_BEAT0 0x170 32 RW 0x00000000 
ECC Reg2aRddatabus_beat0
ECC_REG2ARDDATABUS_BEAT1 0x174 32 RW 0x00000000 
ECC Reg2Rddatabus_beat1
ECC_REG2ARDDATABUS_BEAT2 0x178 32 RW 0x00000000 
ECC Reg2Rddatabus_beat2
ECC_REG2ARDDATABUS_BEAT3 0x17C 32 RW 0x00000000 
ECC Reg2Rddatabus_beat3
ECC_ERRGENHADDR_0 0x180 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_1 0x184 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_2 0x188 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_3 0x18C 32 RO 0x00000000 
Error address register
DERRHADDR 0x1B0 32 RO 0x00000000 
Double-bit error high address
SERRHADDR 0x1B4 32 RO 0x00000000 
Single-bit error address
AUTOWB_CORRHADDR 0x1BC 32 RO 0x00000000 
This register shows the high address of the current autoWB correction SBE.
MPFE_HMCA_CTRL 0x210 32 RW 0x00000000 
MPFE-HMCA-CTRL config+status register
RSTHANDSHAKECTRL 0x214 32 RW 0x00000000 
reset handshaking from MPFE or ARM
RSTHANDSHAKESTAT 0x218 32 RO 0x00000000 
Reset handshaking from IO48 or Nios
MPR_9BEAT1 0x21C 32 RO 0x00000000 
MPR register [319:288] for first beat
MPR_10BEAT1 0x220 32 RO 0x00000000 
MPR register [351:320] for first beat
MPR_11BEAT1 0x224 32 RO 0x00000000 
MPR register [383:352] for first beat
MPR_12BEAT1 0x228 32 RO 0x00000000 
MPR register [415:384] for first beat
MPR_13BEAT1 0x22C 32 RO 0x00000000 
MPR register [447:416] for first beat
MPR_14BEAT1 0x230 32 RO 0x00000000 
MPR register [479:448] for first beat
MPR_15BEAT1 0x234 32 RO 0x00000000 
MPR register [511:480] for first beat
MPR_16BEAT1 0x238 32 RO 0x00000000 
MPR register [543:512] for first beat
MPR_17BEAT1 0x23C 32 RO 0x00000000 
MPR register [575:544] for first beat
ECC_REG2BWRECCDATABUS 0x264 32 RW 0x00000000 
ECC [Upper] from register associated to data which will be written to the RAM
ECC_REG2BRDECCDATABUS 0x268 32 RW 0x00000000 
ECC [Upper] from register associated to RD data which will be written to hmc ecc
ECC_ERRGENADDR_4 0x26C 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_5 0x270 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_6 0x274 32 RO 0x00000000 
Error address register
ECC_ERRGENADDR_7 0x278 32 RO 0x00000000 
Error address register
ECC_REG2BRDDATABUS_BEAT0 0x27C 32 RW 0x00000000 
ECC Reg2bRddatabus_beat0
ECC_REG2BRDDATABUS_BEAT1 0x280 32 RW 0x00000000 
ECC Reg2Rddatabus_beat1
ECC_REG2BRDDATABUS_BEAT2 0x284 32 RW 0x00000000 
ECC Reg2Rddatabus_beat2
ECC_REG2BRDDATABUS_BEAT3 0x288 32 RW 0x00000000 
ECC Reg2Rddatabus_beat3
ECC_ERRGENHADDR_4 0x28C 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_5 0x290 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_6 0x294 32 RO 0x00000000 
Error address register
ECC_ERRGENHADDR_7 0x298 32 RO 0x00000000 
Error address register
MPR_9BEAT2 0x29C 32 RO 0x00000000 
MPR register [319:288] for second beat
MPR_10BEAT2 0x2A0 32 RO 0x00000000 
MPR register [351:320] for second beat
MPR_11BEAT2 0x2A4 32 RO 0x00000000 
MPR register [383:352] for second beat
MPR_12BEAT2 0x2A8 32 RO 0x00000000 
MPR register [415:384] for second beat
MPR_13BEAT2 0x2AC 32 RO 0x00000000 
MPR register [447:416] for second beat
MPR_14BEAT2 0x2B0 32 RO 0x00000000 
MPR register [479:448] for second beat
MPR_15BEAT2 0x2B4 32 RO 0x00000000 
MPR register [511:480] for second beat
MPR_16BEAT2 0x2B8 32 RO 0x00000000 
MPR register [543:512] for second beat
MPR_17BEAT2 0x2BC 32 RO 0x00000000 
MPR register [575:544] for second beat
IOHMC_STAT 0x2C0 32 RW 0x00000000 
IOHMC status register
ECC_RDECCDATA2AREGBUS_BEAT0 0x2C4 32 RO 0x00000000 
ECC of data[Lower] from DRAM will be written to register
 - x64:         full data
 - x32, x16: beat-0 data
ECC_RDECCDATA2AREGBUS_BEAT1 0x2C8 32 RO 0x00000000 
ECC of data[Lower] from DRAM will be written to register
  - x32, x16: beat-1 data
ECC_RDECCDATA2AREGBUS_BEAT2 0x2CC 32 RO 0x00000000 
ECC of data[Lower] from DRAM will be written to register
 - x16: beat-2 data
ECC_RDECCDATA2AREGBUS_BEAT3 0x2D0 32 RO 0x00000000 
ECC of data[Lower] from DRAM will be written to register
 - x16: beat-3 data
ECC_RDECCDATA2BREGBUS_BEAT0 0x2D4 32 RO 0x00000000 
ECC of data[Upper] from DRAM will be written to register
 - x64:         full data
 - x32, x16: beat-0 data
ECC_RDECCDATA2BREGBUS_BEAT1 0x2D8 32 RO 0x00000000 
ECC of data[Upper] from DRAM will be written to register
  - x32, x16: beat-1 data
ECC_RDECCDATA2BREGBUS_BEAT2 0x2DC 32 RO 0x00000000 
ECC of data[Upper] from DRAM will be written to register
 - x16: beat-2 data
ECC_RDECCDATA2BREGBUS_BEAT3 0x2E0 32 RO 0x00000000 
ECC of data[Upper] from DRAM will be written to register
 - x16: beat-3 data