INTSTAT 

         Interrupt status
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011120

Size: 32

Offset: 0x120

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

DERRBUSFLG

0x0

ADDRPARFLG

0x0

ADDRMTCFLG

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SEQ2CORE_PENA

0x0

HMI_PENA

0x0

DERRPENA

0x0

SERRPENA

0x0

INTSTAT Fields

Bit Name Description Access Reset
18 DERRBUSFLG 
This bit is used to flag the last transaction was flagged with double-bit error.
1'b0: no effect.
1'b1: indicates double-bit error has occured. This will drive the bus to respond the read with bus error. Write of one will clear this register double-but bus error. 
Bus error occurs as part of the transaction but this indicates the SW the cause of the error. This should only occur once per transaction
 RW 0x0
17 ADDRPARFLG 
External address parity flag for DDR4 memory.
This bit is used to flag external address parity flag which is driven with derr_req port.
1'b0: No Effect. 
1'b1: Read of one indicates double-bit interrupt has occurred.   Write of one will clear this register last address parity flag.
RW 0x0
16 ADDRMTCFLG 
Address mismatch error flag.
This bit is used to flag the last transaction was flagged with address mismatch error.
1'b0: No effect.
1'b1: indicates address mismatch error has occured. This will drive the bus to respond the read with bus error. Write of one will clears this register address mismatch error.
Bus error occurs as part of the transaction but this indicates the SW the cause of the error. This should occur once per transaction.
 RW 0x0
3 SEQ2CORE_PENA 
SEQ2CORE pending
This bit is used to clear the pending SEQ2CORE.
1'b0: No effect
1'b1: indicates seq2core interrupt is pending. Write of one will clear the pending interrupt. This will de-assert the seq2core_intr signal.
RW 0x0
2 HMI_PENA 
HMI interrupt pending
This bit is used to clear the pending hmi interrupt bit.
1'b0: No effect
1'b1: indicates hmi interrupt is pending. Write of one will clear the pending interrupt. This will de-assert the hmi_intr signal.
 RW 0x0
1 DERRPENA 
Double bit error pending
This bit is used to clear the pending DBE.
1'b0: No effect.
1'b1: indicates DBE is pending. Write of one will clear the pending DBE. This will de-assert the derr_req signal.
 RW 0x0
0 SERRPENA 
Single-bit error pending
This bit is used to clear the pending SBE.
1'b0: No effect.
1'b1: indicates SBE is pending. Write of one will clear the pending. This will de-assert the serr_req signal.
 RW 0x0