ECC_REG2BRDECCDATABUS

         ECC [Upper] from register associated to RD data which will be written to hmc ecc

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF8011268`

Size: 32

Offset: 0x268

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ECC7BUS` `0x0`								`ECC6BUS` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ECC5BUS` `0x0`								`ECC4BUS` `0x0`

ECC_REG2BRDECCDATABUS Fields

Bit	Name	Description	Access	Reset
31:24	`ECC7BUS`	ECC from register associated to RD data [255:192] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero.	`RW`	`0x0`
23:16	`ECC6BUS`	ECC from register associated to RD data [191:128] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero.	`RW`	`0x0`
15:8	`ECC5BUS`	ECC from register associated to RD data [127:64] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero.	`RW`	`0x0`
7:0	`ECC4BUS`	ECC from register associated to RD data [63:0] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero.	`RW`	`0x0`