DDRIOCTRL
DDR IO Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_hmc_adp_csr_inst_0_ocp_slv_block | 0xF8011000 | 0xF8011008 |
Size: 32
Offset: 0x8
Access: RW
Access mode: PRIVILEGEMODE
Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
MPFE_HMCA_DATA_RATE 0x0 |
IO_SIZE 0x0 |
|||||||||||||
DDRIOCTRL Fields
| Bit | Name | Description | Access | Reset | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | MPFE_HMCA_DATA_RATE |
Configuration of MPFE-HMCA operating clock/data-rate relative to DDR Clock/Data rate. Clock is driven from IO96/IOHMC PLL into MPFE. These bits are configured at start to indicate MPFE-HMCA clock/data-rate operation relative to DDR clock rate [DDR data rate is 2x]. Note that this bit is used for MPFE-HMCA logic only – it does not control the IO96 or any other aspect of the system. MPFE-HMCA defaults to haf-rate operation. 0 = MPFE-HMCA Half-rate mode [256b AvST data packet @ DDR-data-rate/4] 1 = MPFE-HMCA Quarter-rate mode [512b AvST data packet @ DDR-data-rate/8]
|
RW | 0x0 | ||||||||
| 1:0 | IO_SIZE |
External Configuration of DDR IO size. These bits are configured at start to indicate the external DDR IO size. 2b00 = DDR IO x16. default value after reset 2b01 = DDR IO x32 2b10 = DDR IO x64
|
RW | 0x0 |