AUTOWB_DROP_CNTREG

         Maximum counter value for AUTOWB correction interrupt

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF8011140`

Size: 32

Offset: 0x140

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`CNT` `0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CNT` `0x1`

AUTOWB_DROP_CNTREG Fields

Bit	Name	Description	Access	Reset
31:0	`CNT`	Compare value for the internal autoWB correction count. This register sets the value to compare with the autoWB internal counter. Software should write to this register before enabling the interrupt on compare. 0x1: If the autoWB_drop_cntreg bits are not modified before enabling the hmi_intr, autoWB internal counter=0 and autoWB_dop_cnt =1, serr compare interrupt will not occur. Default after reset. Nonzero: if autoWB internal counter == autoWB_drop_cnt == nonzero will create a serr compare interrupt. When the compare matches, autoWB_drop_flg will be set.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

31:0

CNT

Compare value for the internal autoWB correction count.
This register sets the value to compare with the autoWB internal counter. Software should write to this register before enabling the interrupt on compare.   
0x1: If the autoWB_drop_cntreg bits are not modified before enabling the hmi_intr, autoWB internal counter=0 and autoWB_dop_cnt =1, serr compare interrupt will not occur. Default after reset.
Nonzero: if autoWB internal counter == autoWB_drop_cnt  == nonzero will create a serr compare interrupt. 
When the compare matches, autoWB_drop_flg will be set.

RW

0x1