MPFE_HMCA_CTRL

         MPFE-HMCA-CTRL config+status register

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF8011210`

Size: 32

Offset: 0x210

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`								`status` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`DISABLE_WR_ECC_INFO_RMW_OPT` `0x0`	`config` `0x0`

MPFE_HMCA_CTRL Fields

Bit	Name	Description	Access	Reset
23:16	`status`	spare status registers	`RO`	`0x0`
8	`DISABLE_WR_ECC_INFO_RMW_OPT`	1'b1: [When set] Disable WR_ECC_INFO modification for RMW performance optimization 1'b0: [Default] Enable WR_ECC_INFO modification for RMW performance optimization Applicable only to x32, x16 modes, where write-bursts are typically >= 2 IOHMC splits up write-bursts larger than 2 beats into smaller beats. wr_ecc_info is normally 0x2 for the beats not being written (example: HR x32, byte-enable = 0xF or QR x16, byte-enable =0x3), IOHMC detects these back-2-back as dummy-writes, and issues RMW.. By enabling WR_ECC_INFO modification based on whther earlier beats have been full-writes, and updatign wr_ecc_info to NORMAL_FULL_WRITE even for the beats with byte-enables all zeroes, these unnecessary dummy writes can be prevented	`RW`	`0x0`
7:0	`config`	spare config registers	`RW`	`0x0`

Bit

Name

Description

Access

Reset

23:16

status

spare status registers

RO

0x0

DISABLE_WR_ECC_INFO_RMW_OPT

1'b1: [When set] Disable WR_ECC_INFO modification for RMW performance optimization
1'b0: [Default]     Enable  WR_ECC_INFO modification for RMW performance optimization

Applicable only to x32, x16 modes, where write-bursts are typically >= 2
IOHMC splits up write-bursts larger than 2 beats into smaller beats. 
wr_ecc_info is normally 0x2 for the beats not being written (example: HR x32, byte-enable = 0xF or QR x16, byte-enable =0x3), 
IOHMC detects these back-2-back as dummy-writes, and issues RMW.. 
By enabling WR_ECC_INFO modification based on whther earlier beats have been full-writes, and updatign wr_ecc_info to NORMAL_FULL_WRITE even for the beats with byte-enables all zeroes, these unnecessary dummy writes can be prevented

RW

0x0

7:0

config

spare config registers

RW

0x0