ECC_DIAGON
Enable diagnostics access
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_hmc_adp_csr_inst_0_ocp_slv_block | 0xF8011000 | 0xF8011150 |
Size: 32
Offset: 0x150
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
ECCDIAGON 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
RDDIAGON 0x0 |
WRDIAGON 0x0 |
|||||||||||||
ECC_DIAGON Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 16 | ECCDIAGON |
ECC diagnostics mode. 1'b0: ECC diagnostics logic is disabled. ECC encoder bypass is disabled. 1'b1: ECC diagnostics logic is enabled. Direction of ECC data from the register to data bus or data bus to ecc register is determined by ECC_rddiagon or ECC_wrdiagon.
|
RW | 0x0 | ||||||
| 1 | RDDIAGON |
Read diagnostics mux enabled. This overrides the data entering the ECC decoder. 1'b0: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is disabled. 1'b1: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is enabled. Both Rddiagon and Wrdiagon bits can be enabled.
|
RW | 0x0 | ||||||
| 0 | WRDIAGON |
Write diagnostics mux enabled. This overrides the encoder output with the register data ecc. 1'b0: Write diagnostics path via the ecc_reg2wdatabus is disabled. 1'b1: Write diagnostics path via the ecc_reg2wdatabus is enabled. Both Rddiagon and Wrdiagon bits can be enabled.
|
RW | 0x0 |