DDRCALSTAT

         DDR Calibration Status Register

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF801100C`

Size: 32

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`FAIL` `0x0`	`CAL` `0x0`

DDRCALSTAT Fields

Bit	Name	Description	Access	Reset
1	`FAIL`	DDR calibration failure status. Indicates whether DDR calibration has failed. 1'b0: Calibration is in progress or did not fail. 1'b1: Calibration failed.	`RO`	`0x0`
0	`CAL`	DDR calibration status. Indicates the DDR calibration was successful. 1'b0: When set to 0, calibration is either on going, hasn't started or failed. 1'b1: When set to 1, calibration has succeeded.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

FAIL

DDR calibration failure status.
Indicates whether DDR calibration has failed. 
1'b0: Calibration is in progress or did not fail.
1'b1: Calibration failed.

RO

0x0

CAL

DDR calibration status.
Indicates the DDR calibration was successful.
1'b0: When set to 0, calibration is either on going, hasn't started or failed.
1'b1: When set to 1, calibration has succeeded.

RO

0x0