GTS HDMI Intel® FPGA IP User Guide

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ID 823533
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. Release Information 4. GTS HDMI Intel® FPGA IP Getting Started 5. GTS HDMI Intel® FPGA IP Hardware Design Examples 6. HDMI Source 7. HDMI Sink 8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 9. HDMI Parameters 10. HDMI Simulation Example 11. GTS HDMI Intel® FPGA IP User Guide Archives 12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
1. GTS HDMI Intel® FPGA IP Quick Reference x
1.1. Terms and Acronyms
3. Release Information x
3.1. Device Family Support 3.2. Feature Support 3.3. Resource Utilization
4. GTS HDMI Intel® FPGA IP Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying IP Parameters and Options
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
6. HDMI Source x
6.1. Source Functional Description 6.2. Source Interfaces 6.3. Source Clock Tree 6.4. Valid Video Data 6.5. Source Deep Color Implementation
6.1. Source Functional Description x
6.1.1. Source Scrambler, TMDS/TERC4 Encoder 6.1.2. Source Video Resampler 6.1.3. Source Window of Opportunity Generator 6.1.4. Source Auxiliary Packet Encoder 6.1.5. Source Auxiliary Packet Generators 6.1.6. Source Auxiliary Data Path Multiplexers 6.1.7. Source Auxiliary Control Port 6.1.8. Source Audio Encoder 6.1.9. TX Core-PHY Interface 6.1.10. I2C Controller
6.1.7. Source Auxiliary Control Port x
6.1.7.1. Source General Control Packet (GCP) 6.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
6.1.8. Source Audio Encoder x
6.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.8.2. Audio Metadata Bundle Bit-Fields
6.1.9. TX Core-PHY Interface x
6.1.9.1. TX Oversampler 6.1.9.2. Clock Enable Generator
7. HDMI Sink x
7.1. Sink Functional Description 7.2. Sink Interfaces 7.3. Sink Clock Tree 7.4. Sink Deep Color Implementation
7.1. Sink Functional Description x
7.1.1. Sink Word Alignment and Channel Deskew 7.1.2. Sink Descrambler, TMDS/TERC4 Decoder 7.1.3. Sink Auxiliary Decoder 7.1.4. Sink Auxiliary Packet Capture 7.1.5. Sink Video Resampler 7.1.6. Sink Auxiliary Data Port 7.1.7. Sink Audio Decoder 7.1.8. Status and Control Data Channel (SCDC) Interface 7.1.9. RX Core-PHY Interface 7.1.10. I2C Target 7.1.11. I2C and EDID RAM Blocks
7.1.6. Sink Auxiliary Data Port x
7.1.6.1. Sink General Control Packet (GCP) 7.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 7.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
7.1.7. Sink Audio Decoder x
7.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 7.1.7.2. Audio Metadata Bundle Bit-Fields
7.1.9. RX Core-PHY Interface x
7.1.9.1. RX Oversampler
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
8.1. HDMI RX with Integrated Transceiver 8.2. HDMI TX with Integrated Transceiver 8.3. Creating Dual Simplex Groups
9. HDMI Parameters x
9.1. HDMI Source Parameters 9.2. HDMI Sink Parameters
1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide

6.1.7. Source Auxiliary Control Port

To simplify the user logic, the source core has control ports to send the most common auxiliary control packets.

These packets are: General Control Packet, Auxiliary Video Information (AVI) InfoFrame, and HDMI Vendor Specific InfoFrame (VSI).

The core sends the default values in the auxiliary packets. The default values allow the core to send video data compatible with the HDMI 1.4b Specification with minimum description.

You can also override the generators using the customized input values. The override values replace the default values when the input checksum is non-zero.

Table 11.  Insertion and Filtration
Auxiliary Packets Insertion/Filtration Frequency of Insertion
General Control Packet (GCP) –

The core always inserts GCP packets from the GCP sideband upon the rising edge of vsync.

The core always removes the GCP in the Auxiliary Data Port.

You must provide the pixel packing and color depth information through the gcp port.

Once per frame.
Auxiliary Video Information (AVI) InfoFrame

info_avi[122]=1'b0

The core inserts info_avi when there is a non-zero bit upon the rising edge of vsync.

The core send default values when all bits are zero. The core filters the AVI InfoFrame packet on the Auxiliary Data Port.

Once per frame.

info_avi[122]=1'b1

The core does not insert info_avi.

The AVI InfoFrame packet on the Auxiliary Data Port passes through.

Vendor Specific InfoFrame (VSI) info_vsi[61]=1'b0

The core inserts info_vsi[60:0] when there is a non-zero bit upon the rising edge of vsync.

The core sends default values when all bits are zero. The core filters the VSI InfoFrame packet on the Auxiliary Data Port.

Once per frame.
info_vsi[61]=1'b1

The core does not insert info_vsi[60:0].

The VSI InfoFrame packet on the Auxiliary Data Port passes through.

Audio Metadata (AM) audio_metadata[165]=1'b0

The core inserts audio_metadata[164:0] when audio_format[3:0] is 3D audio or MST audio upon the rising edge of vsync.

The core filters the AM packet on the Auxiliary Data Port.

 Once per frame.
audio_metadata[165]=1'b1

The core does not insert audio_metadata[164:0].

The AM packet on the Auxiliary Data Port passes through.
Audio InfoFrame (AI) audio_info_ai[48]=1'b0

The core inserts audio_info_ai[47:0] when there is a non-zero bit upon the rising edge of vsync.

The core sends default values when all bits are zero. The core filters the AI packet on the Auxiliary Data Port.

Once per frame.
audio_info_ai[48]=1'b1

The core does not insert audio_info_ai[47:0].

The AI packet on the Auxiliary Data Port passes through.
Audio Control Regeneration (ACR) –

The core always inserts the audio_N and audio_CTS.

The core does not filter the ACR packet in the auxiliary. If there is ACR packet in the Auxiliary Data Port, you must remove it before passing into the Auxiliary Data Port.

Every 1 ms.
Audio Sample –

The core always inserts audio_data.

The core does not filter the audio sample packet in the Auxiliary Data Port. If there is audio sample packet in the Auxiliary Data Port, you must remove it before passing into the Auxiliary Data Port.

Based on audio sample rate.

Section Content
Source General Control Packet (GCP)
Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields
Source HDMI Vendor Specific InfoFrame (VSI)

Related Information
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