GTS HDMI Intel® FPGA IP User Guide

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ID 823533
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. Release Information 4. GTS HDMI Intel® FPGA IP Getting Started 5. GTS HDMI Intel® FPGA IP Hardware Design Examples 6. HDMI Source 7. HDMI Sink 8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 9. HDMI Parameters 10. HDMI Simulation Example 11. GTS HDMI Intel® FPGA IP User Guide Archives 12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
1. GTS HDMI Intel® FPGA IP Quick Reference x
1.1. Terms and Acronyms
3. Release Information x
3.1. Device Family Support 3.2. Feature Support 3.3. Resource Utilization
4. GTS HDMI Intel® FPGA IP Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying IP Parameters and Options
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
6. HDMI Source x
6.1. Source Functional Description 6.2. Source Interfaces 6.3. Source Clock Tree 6.4. Valid Video Data 6.5. Source Deep Color Implementation
6.1. Source Functional Description x
6.1.1. Source Scrambler, TMDS/TERC4 Encoder 6.1.2. Source Video Resampler 6.1.3. Source Window of Opportunity Generator 6.1.4. Source Auxiliary Packet Encoder 6.1.5. Source Auxiliary Packet Generators 6.1.6. Source Auxiliary Data Path Multiplexers 6.1.7. Source Auxiliary Control Port 6.1.8. Source Audio Encoder 6.1.9. TX Core-PHY Interface 6.1.10. I2C Controller
6.1.7. Source Auxiliary Control Port x
6.1.7.1. Source General Control Packet (GCP) 6.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
6.1.8. Source Audio Encoder x
6.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.8.2. Audio Metadata Bundle Bit-Fields
6.1.9. TX Core-PHY Interface x
6.1.9.1. TX Oversampler 6.1.9.2. Clock Enable Generator
7. HDMI Sink x
7.1. Sink Functional Description 7.2. Sink Interfaces 7.3. Sink Clock Tree 7.4. Sink Deep Color Implementation
7.1. Sink Functional Description x
7.1.1. Sink Word Alignment and Channel Deskew 7.1.2. Sink Descrambler, TMDS/TERC4 Decoder 7.1.3. Sink Auxiliary Decoder 7.1.4. Sink Auxiliary Packet Capture 7.1.5. Sink Video Resampler 7.1.6. Sink Auxiliary Data Port 7.1.7. Sink Audio Decoder 7.1.8. Status and Control Data Channel (SCDC) Interface 7.1.9. RX Core-PHY Interface 7.1.10. I2C Target 7.1.11. I2C and EDID RAM Blocks
7.1.6. Sink Auxiliary Data Port x
7.1.6.1. Sink General Control Packet (GCP) 7.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 7.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
7.1.7. Sink Audio Decoder x
7.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 7.1.7.2. Audio Metadata Bundle Bit-Fields
7.1.9. RX Core-PHY Interface x
7.1.9.1. RX Oversampler
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
8.1. HDMI RX with Integrated Transceiver 8.2. HDMI TX with Integrated Transceiver 8.3. Creating Dual Simplex Groups
9. HDMI Parameters x
9.1. HDMI Source Parameters 9.2. HDMI Sink Parameters
1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide

7.3. Sink Clock Tree

The sink core uses various clocks.

The logic clocks the transceiver data into the core using the three CDR clocks: (rx_clk[2:0]).

The TMDS and TERC4 decoding is done at the transceiver recovered clock.

The pixel data clock depends on the video format used (within HDMI specification).

Figure 38. Sink Clock TreeThe figure shows how the different clocks connect in the sink core.

For HDMI sink, you must instantiate three receiver channels to receive data in TMDS mode.

Figure 39. Sink Clock Tree

The transceiver RX CDR has reference clock 0, which is supplied with TMDS clock from the HDMI connector.

A general-purpose phase-locked loop GPLL that is referenced by the transceiver output clock, is used to generate the FRL (frl_clk) clock. You can fix vid_clk at a static frequency of 300 MHz.

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