GTS HDMI Intel® FPGA IP User Guide

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ID 823533
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. Release Information 4. GTS HDMI Intel® FPGA IP Getting Started 5. GTS HDMI Intel® FPGA IP Hardware Design Examples 6. HDMI Source 7. HDMI Sink 8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 9. HDMI Parameters 10. HDMI Simulation Example 11. GTS HDMI Intel® FPGA IP User Guide Archives 12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
1. GTS HDMI Intel® FPGA IP Quick Reference x
1.1. Terms and Acronyms
3. Release Information x
3.1. Device Family Support 3.2. Feature Support 3.3. Resource Utilization
4. GTS HDMI Intel® FPGA IP Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying IP Parameters and Options
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
6. HDMI Source x
6.1. Source Functional Description 6.2. Source Interfaces 6.3. Source Clock Tree 6.4. Valid Video Data 6.5. Source Deep Color Implementation
6.1. Source Functional Description x
6.1.1. Source Scrambler, TMDS/TERC4 Encoder 6.1.2. Source Video Resampler 6.1.3. Source Window of Opportunity Generator 6.1.4. Source Auxiliary Packet Encoder 6.1.5. Source Auxiliary Packet Generators 6.1.6. Source Auxiliary Data Path Multiplexers 6.1.7. Source Auxiliary Control Port 6.1.8. Source Audio Encoder 6.1.9. TX Core-PHY Interface 6.1.10. I2C Controller
6.1.7. Source Auxiliary Control Port x
6.1.7.1. Source General Control Packet (GCP) 6.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
6.1.8. Source Audio Encoder x
6.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.8.2. Audio Metadata Bundle Bit-Fields
6.1.9. TX Core-PHY Interface x
6.1.9.1. TX Oversampler 6.1.9.2. Clock Enable Generator
7. HDMI Sink x
7.1. Sink Functional Description 7.2. Sink Interfaces 7.3. Sink Clock Tree 7.4. Sink Deep Color Implementation
7.1. Sink Functional Description x
7.1.1. Sink Word Alignment and Channel Deskew 7.1.2. Sink Descrambler, TMDS/TERC4 Decoder 7.1.3. Sink Auxiliary Decoder 7.1.4. Sink Auxiliary Packet Capture 7.1.5. Sink Video Resampler 7.1.6. Sink Auxiliary Data Port 7.1.7. Sink Audio Decoder 7.1.8. Status and Control Data Channel (SCDC) Interface 7.1.9. RX Core-PHY Interface 7.1.10. I2C Target 7.1.11. I2C and EDID RAM Blocks
7.1.6. Sink Auxiliary Data Port x
7.1.6.1. Sink General Control Packet (GCP) 7.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 7.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
7.1.7. Sink Audio Decoder x
7.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 7.1.7.2. Audio Metadata Bundle Bit-Fields
7.1.9. RX Core-PHY Interface x
7.1.9.1. RX Oversampler
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
8.1. HDMI RX with Integrated Transceiver 8.2. HDMI TX with Integrated Transceiver 8.3. Creating Dual Simplex Groups
9. HDMI Parameters x
9.1. HDMI Source Parameters 9.2. HDMI Sink Parameters
1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide

7.2. Sink Interfaces

The following tables list the port interfaces of the sink.
Table 45.  Sink Reset Interface
Port Type Clock Domain Port Direction Description
Reset — reset Input Main asynchronous reset input.
Note: Asserting the reset input resets the SCDC register.
Reset — reset_vid Input Reset input for the video domain.
Table 46.  Sink Clock Interface
Port Type Clock Domain Port Direction Description
Clock — vid_clk Input Video data clock input.

vid_clk frequency = 300 MHz.

  • vid_clk runs at the maximum frequency across all resolutions and FRL rates.
  • The video data is qualified by the vid_valid signal.
  • vid_clk can be asynchronous to ls_clk and frl_clk.
Clock — clk_b Input

Transceiver recovered clock from the "Blue" data channel.

Clock — clk_g Input

Transceiver recovered clock from the "Green" data channel.

Clock — clk_r Input

Transceiver recovered clock from the "Red" data channel.

Clock — clk_c Input

Transceiver recovered clock from the clock data channel.

Clock — i2c_clk Input Avalon-MM SCDC Management Interface clock input.
Table 47.  Sink Video Data Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit vid_clk vid_data[N*48-1:0] Output

Video 48-bit pixel data output port. For N pixels per clock, this port produces N 48-bit pixels per clock.

Conduit vid_clk vid_de[N-1:0] Output Video data enable output that indicates active picture region.
Conduit vid_clk vid_hsync[N-1:0] Output Video horizontal sync output.
Conduit vid_clk vid_vsync[N-1:0] Output Video vertical sync output.
Conduit vid_clk vid_valid Output

Indicates if the video data is valid. When in TMDS mode and vid_clk is running at the actual pixel clock, this signal should always be asserted.

When you generate the video data at a frequency higher than the actual pixel clock, use vid_valid to qualify the validity of the video data. vid_valid and vid_clk guarantee the exact pixel clock rate.

Conduit vid_clk locked Output

Indicates that the HDMI sink core is locked to the TMDS signals with successful lane deskew and word alignment.

Note: The locked[2:0] signal is 3 bits wide for Quartus® Prime Pro Edition software versions 19.2 and earlier, where each bit represents the locked status of a TMDS color channel.
Conduit vid_clk vid_lock Output Asserted when the length or duration of vid_de is consistent for 3 frames. If the length or duration of vid_de is inconsistent for 2 frames, this signal deasserts.
Table 48.  Sink Data Port Interface
Port Type Clock Domain Port Direction Description
Connect to the transceiver data output if no oversampling is required.

If oversampling is required, the port should connect to a DCFIFO and an oversampling user logic before connecting to a transceiver data output.

Refer to Sink Clock Tree for more information.

Conduit

clk_b

in_b[transceiver width-1:0] Input TMDS encoded blue channel (0) input.

This signal is TMDS encoded blue channel (0) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit clk_b in_g[transceiver width-1:0] Input TMDS encoded green channel (1) input.

This signal is TMDS encoded green channel (1) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit clk_b in_r[transceiver width-1:0] Input TMDS encoded red channel (2) input.

This signal is TMDS encoded red channel (2) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit clk_c in_c[transceiver width-1:0] Input

This signal is unused.

Transceiver width is configured to 40 bits.

Conduit clk_b in_lock Input

Indicates the HDMI RX core is ready to operate. This signal should be driven by the ready signal from the transceiver reset controller that indicates transceiver are locked.

Table 49.  Sink Decoder Status Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit clk_b ctrl[N*6-1:0] Output DVI (mode = 0) status signals that overwrite the control and synchronization character in the green and red channels.
Bit-Field n=0,1.....N-1

n*6+5

CTL3

n*6+4

CTL2

n*6+3

CTL1

n*6+2

CTL0

n*6+1

Reserved (0)

n*6

Reserved (0)

Refer to the HDMI 1.4b Specification for more information.

Conduit clk_b mode Output

Indicates the encoding mode of the incoming TMDS signals.

  • 0: DVI
  • 1: HDMI
Table 50.  Sink SCDC Control Port Interface
Port Type Clock Domain Port Direction Description
Conduit i2c_clk in_5v_power Input Detects the presence of 5V input voltage.
Conduit i2c_clk rx_hpd_req Output Indicates the Hot Plug Detect (HPD) status. This signal should be driven to the HPD pin on the HDMI connector.
  • Sink deasserts rx_hpd_req if in_5v_power is low or after reset.
  • Sink will assert rx_hpd_req after 1 second in_5v_power is detected, or after reset
  • Contact your Intel Sales representative if you want to change the HPD duration.
Conduit i2c_clk TMDS_Bit_clock_Ratio Output

Indicates if the TMDS Bit Rate is greater than 3.4 Gbps

  • 0: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 10
  • 1: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 40
Table 51.  Sink Avalon-MM SCDC Management Interface Interface
Port Type Clock Domain Port Direction Description
Refer to HDMI 2.0b Specification Section 10.4 for address and data bit mapping.
Avalon® memory-mapped interface i2c_clk scdc_i2c_addr[7:0] Input Address.
Avalon® memory-mapped interface i2c_clk scdc_i2c_r Input Assert to indicate a read transfer.
Avalon® memory-mapped interface i2c_clk scdc_i2c_rdata[7:0] Output Data driven from the core in response to a read transfer.
Avalon® memory-mapped interface i2c_clk scdc_i2c_w Input Assert to indicate a write transfer.
Avalon® memory-mapped interface i2c_clk scdc_i2c_wdata[7:0] Input Data for write transfers.
Table 52.  Sink Auxiliary Data Port Interface
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary parameter3
Conduit aux_clk aux_valid Output Auxiliary data channel valid output to qualify the data.
Conduit aux_clk aux_data[71:0] Output Auxiliary data channel data output.

For information about the bit-fields, refer to Sink Auxiliary Decoder.

Conduit aux_clk aux_sop Output Auxiliary data channel start-of-packet output to mark the beginning of a packet.
Conduit aux_clk aux_eop Output Auxiliary data channel end-of-packet output to mark the end of a packet.
Conduit aux_clk aux_error Output Asserted when there is auxiliary data channel CRC error.
Table 53.  Sink Auxiliary Status Port Interface
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary parameter 3
Conduit aux_clk gcp[5:0] Output General Control Packet output.

For information about the bit-fields, refer to Source General Control Packet (GCP) Bit-Fields.

Conduit aux_clk

info_avi[122:0] (

Output Auxiliary Video Information InfoFrame output.

For information about the bit-fields, refer to Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields .

Conduit aux_clk info_vsi[60:0] Output Vendor Specific Information InfoFrame output.
For information about the bit-fields, refer to Source HDMI Vendor Specific InfoFrame Bit-Fields.
Table 54.  Sink Auxiliary Memory Interface Interface
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary parameter 3
Conduit aux_clk aux_pkt_addr[6:0] Output Auxiliary packet memory buffer address output.
Conduit aux_clk aux_pkt_data[71:0] Output Auxiliary packet memory buffer data output.
Conduit aux_clk aux_pkt_wr Output Auxiliary packet memory buffer write strobe output.
Table 55.  Sink Audio Port Interface
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary and Support audio 3
Conduit aux_clk audio_CTS[19:0] Output Audio CTS value output.
Conduit aux_clk audio_N[19:0] Output Audio N value output.
Conduit aux_clk audio_data[255:0] Output Audio data output.

For audio channel values, refer to Audio Channels.

Conduit aux_clk audio_de Output Audio data valid output.
Conduit aux_clk audio_metadata[164:0] Output Additional information related to 3D audio and MST audio.

For information about the bit-fields, refer to Audio Metadata Bundle Bit-Fields for Packet Header and Control, Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO = 1, and Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO=0.

Conduit aux_clk audio_format[4:0] Output Indicates 3D audio status and the audio format detected.
Bit-Field Description
4 The core asserts to indicate the first 8 channels of each 3D audio sample.
3:0

For information about the bit-fields, refer to Definition of the Supported audio_format[3:0].

 
Conduit aux_clk audio_info_ai[47:0] Output Audio InfoFrame output bundle.

For information about the bit-fields, refer to Source Audio InfoFrame Bundle Bit-Fields.

Table 56.  Sink PHY Control Interface Port Interface
Port Type Clock Domain Port Direction Description
Conduit clk_b os Input

Indicates to the core that the current receiving data rate requires downsampling with a factor of 5.

Assert this signal when the receiving TMDS Bit Rates is less than 1 Gbps.

Table 57.  Sink I2C Target Interface Port Interface
Port Type Clock Domain Port Direction Description
Conduit — i2c_scl Input

SCL signal from I2C bus on the HDMI connector.

This signal is not available if you turn off the Include I2C parameter.

Conduit — i2c_sda Inout

SDA signal from I2C bus on the HDMI connector.

This signal is not available if you turn off the Include I2C or Include I2C Pads parameter.

Conduit — i2c_sda_in Input SDA input signal from the HDMI connector I2C tri-stateable I/O pad.
Note: This signal is only available when you turn off the Include I2C Pads parameter.
Conduit — i2c_sda_oe Output

SDA output enable signal to the HDMI connector I2C tri-stateable I/O pad.

1: SDA pulled low

0: Output buffer tri-stated and SDA externally pulled high
Note: This signal is only available when you turn off the Include I2C Pads parameter.
  i2c_clk edid_i2cslv_rdata[7:0] Input

Connect this signal to the output q port of an EDID RAM. This signal returns the value from a certain address in the RAM to the internal I2C target.

This signal is available only if you turn on the Include I2C parameter and turn off the Include EDID RAM parameter.

Conduit i2c_clk edid_i2cslv_addr[31:0] Output

Connect this signal to the output address port of an EDID RAM. This signal indicates the address that the I2C target would access to the RAM.

This signal is available only if you turn on the Include I2C target parameter and turn off the Include EDID RAM parameter.

Conduit i2c_clk tmds_config_trans_det Output

Indicates that there is a new write operation to the SCDC address offset 0x20 (TMDS configuration).

Connect this signal to a reconfiguration controller to restart the reconfiguration flow.

This signal is not available if you turn off the Include I2C parameter.

Table 58.  Sink EDID RAM Interface Port Interface
Port Type Clock Domain Port Direction Description
Conduit i2c_clk edid_ram_access Input

Assert this signal when you are reading or writing to the EDID RAM. Deassert this signal when the read and write operations are complete.

Asserting this signal would trigger an HPD event to the source. When you deassert this signal, the source reads the new EDID which you have just written into the RAM.

This signal is not available if you turn off the Include EDID RAM parameter.

Avalon® -MM i2c_clk edid_ram_address Input

Avalon® memory mapped interface to the EDID RAM. Connect these signals to an Avalon® memory mapped host, such as Nios® , to perform read and write operation to the EDID RAM.

These signals are not available if you turn off the Include EDID RAM parameter.

Avalon® -MM i2c_clk edid_ram_read Input
Avalon® -MM i2c_clk edid_ram_write Input
Avalon® -MM i2c_clk edid_ram_waitrequest Output
Avalon® -MM i2c_clk edid_ram_readdata[7:0] Output
Avalon® -MM i2c_clk edid_ram_writedata[7:0] Input
Related Information
3

aux_clk = vid_clk

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