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1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
6.1.1. Source Scrambler, TMDS/TERC4 Encoder
6.1.2. Source Video Resampler
6.1.3. Source Window of Opportunity Generator
6.1.4. Source Auxiliary Packet Encoder
6.1.5. Source Auxiliary Packet Generators
6.1.6. Source Auxiliary Data Path Multiplexers
6.1.7. Source Auxiliary Control Port
6.1.8. Source Audio Encoder
6.1.9. TX Core-PHY Interface
6.1.10. I2C Controller
7.1.1. Sink Word Alignment and Channel Deskew
7.1.2. Sink Descrambler, TMDS/TERC4 Decoder
7.1.3. Sink Auxiliary Decoder
7.1.4. Sink Auxiliary Packet Capture
7.1.5. Sink Video Resampler
7.1.6. Sink Auxiliary Data Port
7.1.7. Sink Audio Decoder
7.1.8. Status and Control Data Channel (SCDC) Interface
7.1.9. RX Core-PHY Interface
7.1.10. I2C Target
7.1.11. I2C and EDID RAM Blocks
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7.1.4. Sink Auxiliary Packet Capture
To simplify user applications and minimize external logic, the core captures 3 different packet types and presents the packets outside the core.
These packets are: General Control Packet (GCP), Auxiliary Video Information (AVI) InfoFrame, and HDMI Vendor Specific InfoFrame (VSI).
The GCP, AVI and VSI bit-fields (excluding control bit) are defined in Source GCP Bit-Fields, Source Auxiliary Video Information (AVI) InfoFrame, and Source HDMI Vendor Specific InfoFrame Bit-Fields respectively with reserved bits return 0.