GTS HDMI Intel® FPGA IP User Guide

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ID 823533
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. Release Information 4. GTS HDMI Intel® FPGA IP Getting Started 5. GTS HDMI Intel® FPGA IP Hardware Design Examples 6. HDMI Source 7. HDMI Sink 8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 9. HDMI Parameters 10. HDMI Simulation Example 11. GTS HDMI Intel® FPGA IP User Guide Archives 12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
1. GTS HDMI Intel® FPGA IP Quick Reference x
1.1. Terms and Acronyms
3. Release Information x
3.1. Device Family Support 3.2. Feature Support 3.3. Resource Utilization
4. GTS HDMI Intel® FPGA IP Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying IP Parameters and Options
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
6. HDMI Source x
6.1. Source Functional Description 6.2. Source Interfaces 6.3. Source Clock Tree 6.4. Valid Video Data 6.5. Source Deep Color Implementation
6.1. Source Functional Description x
6.1.1. Source Scrambler, TMDS/TERC4 Encoder 6.1.2. Source Video Resampler 6.1.3. Source Window of Opportunity Generator 6.1.4. Source Auxiliary Packet Encoder 6.1.5. Source Auxiliary Packet Generators 6.1.6. Source Auxiliary Data Path Multiplexers 6.1.7. Source Auxiliary Control Port 6.1.8. Source Audio Encoder 6.1.9. TX Core-PHY Interface 6.1.10. I2C Controller
6.1.7. Source Auxiliary Control Port x
6.1.7.1. Source General Control Packet (GCP) 6.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
6.1.8. Source Audio Encoder x
6.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.8.2. Audio Metadata Bundle Bit-Fields
6.1.9. TX Core-PHY Interface x
6.1.9.1. TX Oversampler 6.1.9.2. Clock Enable Generator
7. HDMI Sink x
7.1. Sink Functional Description 7.2. Sink Interfaces 7.3. Sink Clock Tree 7.4. Sink Deep Color Implementation
7.1. Sink Functional Description x
7.1.1. Sink Word Alignment and Channel Deskew 7.1.2. Sink Descrambler, TMDS/TERC4 Decoder 7.1.3. Sink Auxiliary Decoder 7.1.4. Sink Auxiliary Packet Capture 7.1.5. Sink Video Resampler 7.1.6. Sink Auxiliary Data Port 7.1.7. Sink Audio Decoder 7.1.8. Status and Control Data Channel (SCDC) Interface 7.1.9. RX Core-PHY Interface 7.1.10. I2C Target 7.1.11. I2C and EDID RAM Blocks
7.1.6. Sink Auxiliary Data Port x
7.1.6.1. Sink General Control Packet (GCP) 7.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 7.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
7.1.7. Sink Audio Decoder x
7.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 7.1.7.2. Audio Metadata Bundle Bit-Fields
7.1.9. RX Core-PHY Interface x
7.1.9.1. RX Oversampler
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
8.1. HDMI RX with Integrated Transceiver 8.2. HDMI TX with Integrated Transceiver 8.3. Creating Dual Simplex Groups
9. HDMI Parameters x
9.1. HDMI Source Parameters 9.2. HDMI Sink Parameters
1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide

9.2. HDMI Sink Parameters

Table 60.  HDMI Sink Parameters
Parameter Value Description
Device family Agilex™ 5 Targeted device family. This parameter inherits the value from the project device.
Direction

Transmitter

Receiver

 Selects HDMI receiver.
Pixels per clock 2 pixels per clock

Determines how many pixels are processed per clock.

When you select HDMI Variant = TMDS only, supports 2 pixels per clock.

Transceiver width 40 bits Determines the required transceiver width. The transceiver width depends on the number of TMDS symbols processed in parallel (symbols per clock).
Enable active video protocol None Determines the input video data format. When set to None, the video input is in clocked video format.
HDMI 2.1 variant TMDS only Sets HDMI variant to TMDS only.
Support auxiliary On, Off Determines if auxiliary channel encoding is included. This parameter is turned on by default.
Support deep color On, Off

Determines if the core can encode deep color formats. This parameter is turned on by default.
Support audio On, Off

Determines if the core can encode audio data.

To enable this parameter, you must also enable the Support auxiliary parameter. This parameter is turned on by default.

Support HDCP 1.4 On, Off

Turn on to enable HDCP 1.4 RX support. This feature is currently not supported on Agilex™ 5 devices.

Support HDCP 2.3 On, Off

Turn on to enable HDCP 2.3 RX support. This feature is currently not supported on Agilex™ 5 devices.

Support HDCP Key Management On, Off

Turn on to enable HDCP key management support. You can only turn this parameter on if the Support HDCP 1.4 or Support HDCP 2.3 parameters are turned on. This feature is currently not supported on Agilex™ 5 devices.

Manufacturer OUI —

The Manufacturer Organizationally Unique Identifier (OUI) assigned to the manufactured device to be written into the SCDC registers of address 0xD0, 0xD1, and 0xD2.

Key in 3 byte hexadecimal data.
Device ID String —

The Device Identification (ID) string to be written into the SCDC registers from addresses 0xD3 to 0xDa.

Use this parameter to identify the sink device. You can key in up to eight ASCII characters. If you use less than eight characters, the unused bytes are set to 0x00.

Hardware Revision —

Indicates the major and minor revisions of the hardware. Key in one byte of integer data.

  • Upper byte represents major revision.
  • Lower byte represents minor revision.

The hardware major revision increments on a major silicon or board revision. The hardware minor revision increments on a minor silicon revision or minor board revision and resets to 0 when the major revision increments.

Include I2C slave On, Off

Turn on to include a pair of I2C targets for EDID and SCDC registers. path.

Include EDID RAM On, Off Turn on to include RAM to store EDID information for RX. 4
EDID RAM size 5 In multiple of 2N

Specifies the memory size in number of N-bit words. The value must be in multiple of 2N.

For example, the default memory size is 256 words which is 28 with N = 8.

The N also determines the width of the address bus of the RAM’s Avalon® memory-mapped interface.

RAM file path5 –

Initial content of the memory. The file must be in .hex or .mif file type.

HPD signal polarity 0, 1 Specifies the polarity of Hot Plug Detect (HPD) signal from the connector.
  • 0: Negative
  • 1: Positive
Note: For Bitec daughter card, always set the polarity to 0.
Include I2C Master/Slave On, Off

Turn on to include I2C targets in the HDMI sink for DDC channel communication.

This provides I2C access for the HDMI source to EDID RAM, and SCDC registers.

Include I2C IO Pads On, Off Turn on to instantiate I2C I/O pads in the RX IP core component. 6
HDMI Wrapper Option
  • HDMI only
  • HDMI and Transceiver
 Determines the selection of HDMI wrapper:
  • To enable standalone HDMI IP, select HDMI only.
  • To add Transceiver IP to HDMI IP, select HDMI and Transceiver.
Transceiver Data Rate 5.94G, 2.97G, 1.485G, 0.7425G, 0.27G Determines the selection of the transceiver static rate.

In Quartus® Prime Pro Edition Version 24.2, only static rate is supported.

Transceiver Analog Parameters Analog RX This parameter is only available when you select the HDMI and Transceiver wrapper option.

For more information, refer to the Analog Parameter Options section in the GTS Transceiver PHY User Guide.

Related Information
4 You can only turn on this parameter if you have turned on the Include I2C slave parameter.
5 This parameter is enabled only if the Include EDID RAM parameter is turned on.
6 This parameter is enabled only if you have turned on the Include I2C Master/Slave parameter.
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