GTS Interlaken Intel® FPGA IP User Guide

Download PDF
ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

4. Functional Description

The GTS Interlaken Intel® FPGA IP provides the functionality described in the Interlaken Protocol Specification, Revision 1.1 .

The GTS Interlaken Intel® FPGA IP supports the following interfaces:

User Data Transfer Interface

The user data transfer interface, also known as application interface, provides up to 256 logical channels of communication to and from the Interlaken link. This interface is similar to the Avalon® Streaming interface that supports data bursts or packets, which are carried in the Interlaken meta frame payload.

Interlaken Link Interface

The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.1. It is the high-speed transceiver interface to an Interlaken link.

Management Interface

The management interface provides access to the Interlaken IP internal status and control registers. This interface does not provide access to the hard PCS registers on the device. This interface complies with the Avalon® Memory-Mapped specification defined in the Avalon Interface Specifications.

Transceiver Control Interfaces

The Interlaken IP provides several interfaces to control the transceiver. The transceiver reconfiguration interface provides access to the registers in the GTS PHY IP. This interface provides direct access to the hard PCS registers on the device. This interface complies with the Avalon® memory-mapped specification defined in the Avalon Interface Specifications.
Figure 6. Block Diagram

Section Content
Datapath Flow
Modes of Operation
Performance
IP Reset
M20K ECC Support
Out-of-Band Flow Control

Level Two Title