GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

5.6. GTS Interlaken IP Reconfiguration Signals

Table 30.  GTS Interlaken IP Reconfiguration Signals
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_clk 1 Input Interlaken Mode Avalon memory-mapped reconfiguration clock
reconfig_reset 1 input Interlaken Mode Avalon memory-mapped reconfiguration reset synchronous to reconfig_clk
reconfig_read 1 input Interlaken Mode Avalon memory-mapped reconfiguration read Command
reconfig_write 1 input Interlaken Mode Avalon memory-mapped reconfiguration write Command
reconfig_address 18 + RECONF_ADDR input Interlaken Mode Avalon memory-mapped transceiver reconfiguration address . 18 bits for Avalon memory-mapped addressing. If lanes are 4; RECONF_ADDR = 2; else if lanes are 6: RECONF_ADDR = 3 else if lanes are 8: RECONF_ADDR =3
reconfig_readdata 32 output. Interlaken Mode Avalon memory-mapped XCVR reconfiguration read data
reconfig_readdatavalid 1 output Interlaken Mode Avalon memory-mapped XCVR reconfiguration read data valid
reconfig_waitrequest 1 Output Interlaken Mode Avalon memory-mapped XCVR reconfiguration wait request
reconfig_writedata 32 input Interlaken Mode Avalon memory-mapped reconfiguration write data
reconfig_byteenable 4 input Interlaken Mode Avalon memory-mapped reconfiguration byte enable
Level Two Title