GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

3. Parameter Settings

You customize the GTS Interlaken Intel® FPGA IP using the IP parameter editor.
Table 10.  Main: General
Parameter Supported Values Default Setting Description
Meta fame length 128-8192 2048

Specifies the meta frame length in 64-bit (8-byte) words. Must be a power of two.

Smaller values shorten the time to achieve lock. Larger values reduce the overhead while transferring data, after the clock data recover (CDR) circuit achieves lock.

Number of lanes

4

8

 8

Specifies the number of lanes available for Interlaken communication.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to the IP Supported Combinations of Number of Lanes and Data Rate table .

Data rate (Gbps)

6.25

12.5

 12.5 Gbps

Specifies the data rate on each lane.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to the IP Supported Combinations of Number of Lanes and Data Rate table.

Transceiver reference clock frequency Multiple

156.25 MHz

Specifies the expected frequency of the pll_ref_clk input clock.

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.

Enable M20K ECC support On

Off

 Off

Specifies whether your Interlaken IP variation supports the ECC feature in the M20K memory blocks that are configured as part of the IP.

Turn this parameter on to enable single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP. This feature enhances data reliability but increases latency and resource utilization.

Enable debug endpoint for Datapath and PMA Avalon® memory-mapped interface

On

Off

 Off When on, the GTS Interlaken Intel FPGA IP includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the PMA interface block. it can perform certain tests and debug functions through JTAG using the System Console. This option may require that you include a jtag_debug link in the system.
Table 11.  In-Band Flow Control
Parameter Supported Values Default Setting Description
Include in-band flow control functionality On

Off

 Off Specifies whether your Interlaken IP includes an in-band flow control block.
Number of calendar pages 1

2

4

8

16

 1

Specifies the number of 16-bit pages of in-band flow control data that your Interlaken IP supports. This parameter is available if you turn on IInclude in-band flow control functionality.

Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpretation of the in-band flow control bits. The IP supports a maximum of 256 channels with in-band flow control.

If your design requires a different number of pages, select the lowest supported number of pages that is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, set this parameter to 4 and use pages 3, 2, and 1 while ignoring page 0.

Table 12.  Transceiver Settings
Transceiver Settings Parameter Supported Values Default Setting Description
TX scrambler seed — 0x3ab1278890105cd

Specifies the initial scrambler state. If you configure a single Interlaken IP on your device, you can use the default value of this parameter.

If you configure multiple Interlaken IPs, you must use a different initial scrambler state for each IP.

Select random values for each Interlaken IP. Each scrambler seed should have an approximately even mix of ones and zeros. The scrambler seeds should differ from the other scramblers in multiple spread out bit positions.

Table 13.  User Data Transfer Interface
Parameter Supported Values Default Setting Description
Transfer mode selection Packet

Interleaved

 Packet Supports two modes for packet transfers and ASIC, ASSP, FPGA, and SoC interoperability.
Number of segments 1,2 1 Enables 1 or 2 segments depending on the total number of words. Only available when you select Interleaved for Transfer mode selection

Section Content
Analog Parameters for GTS IPs

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