GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

4.2.1. Interleaved and Packet Modes

You can configure the Interlaken IP to accept interleaved data transfers from the application on the TX user data transfer interface, or to not accept interleaved data transfers on this interface. If the IP can accept interleaved data transfers, it is in interleaved mode. If the IP does not accept interleaved data transfers, it is in packet mode.

The value you specify for the Transfer mode selection parameter in the IP parameter editor determines the IP transmit mode.

In Packet mode, the Interlaken IP performs Optional Scheduling Enhancement based on Section 5.3.2.1.1 of the Interlaken Protocol Specification, Revision 1.1. The IP ignores the itx_sob and itx_eob signals. Instead, the IP performs optional enhanced scheduling based on the settings of BurstMax and BurstMin.

In Interleaved mode, you can achieve full capability of channelization and per-channel flow control offered by the Interlaken IP In this mode, you can interleave bursts of different channels. It allows more efficient use of bandwidth. The Interlaken IP inserts burst control words on the Interlaken link based on the itx_sob and itx_eob inputs. The internal optional enhanced scheduling is disabled and the BurstMax and BurstMin values are ignored. BurstShort is still in effect. To avoid overflowing the transmit FIFO, you should not send a burst that is longer than 1024 bytes.

In Interleaved mode or in Packet mode, the Interlaken IP can accept non-interleaved data on the TX user data transfer interface (itx_din_words). However, if the IP is in Interleaved mode, the application must drive the itx_sob and itx_eob inputs correctly.

In Interleaved mode or in Packet mode, the Interlaken IP can generate interleaved data transfers on the RX user data transfer interface (irx_dout_words). The application must be able to accept interleaved data transfers if the Interlaken link partner transmits them on the Interlaken link. In this case, the Interlaken link partner must send traffic in Interleaved mode that confirms with the Interlaken IP BurstShort value.

Note: The transmitter (link partner) needs to send packets with a minimum packet size of 64 bytes.

Section Content
Transmit User Data Interface Examples
Receive User Data Interface Examples

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