Visible to Intel only — GUID: cxa1690828604565
Ixiasoft
Visible to Intel only — GUID: cxa1690828604565
Ixiasoft
2.3. Tensor Mode
In Tensor mode, there are two DOT engines arranged as two columns. Each column contains ten 8x8 bit fixed-point multipliers. Two pre-loadable ping-pong buffers are available per column to store coefficient values. These coefficients are fed to one side of each multiplier, while the other side receives data from a shared set of ten, 8-bit data buses.
A load_buf_sel signal controls which set of coefficients is active. This allows one set to be updated using the ping-pong buffers while the other set is being used for computations. The DOT product outputs from each column are fed into independent accumulators that offer three different modes of operation. The Tensor floating-point mode utilizes a shared exponent for both the data inputs and the ping-pong buffers. Refer to Operational Modes for Tensor Mode for more information.
Section Content
Input Register Bank for Tensor Mode
DOT Product Vector Engines for Tensor Mode
Pipeline Registers for Tensor Mode
Fixed-point to Floating-point Converter for Tensor Mode
Cascade Input and Datapath Registers for Tensor Mode
Dynamic Control Multiplexer Bank for Tensor Mode
Accumulator for Tensor Mode
Output Registers for Tensor Mode