Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813968
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Variable Precision DSP Blocks Overview 2. Agilex™ 5 Variable Precision DSP Blocks Architecture 3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes 4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations 5. Native Fixed Point DSP Agilex™ FPGA IP Core References 6. Multiply Adder Intel® FPGA IP Core References 7. ALTMULT_COMPLEX Intel® FPGA IP Core References 8. LPM_MULT Intel® FPGA IP Core References 9. LPM_DIVIDE (Divider) Intel FPGA IP Core 10. Native Floating Point DSP Agilex™ FPGA IP References 11. Native AI Optimized DSP Agilex™ FPGA IP References 12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide
1. Agilex™ 5 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Agilex™ 5 Devices
1.2. Supported Operational Modes in Agilex™ 5 Devices x
1.2.1. Fixed-point Arithmetic 1.2.2. Floating-point Arithmetic
2. Agilex™ 5 Variable Precision DSP Blocks Architecture x
2.1. Fixed-point Arithmetic 2.2. Floating-point Arithmetic 2.3. Tensor Mode
2.1. Fixed-point Arithmetic x
2.1.1. Input Register Bank for Fixed-point Arithmetic 2.1.2. Pipeline Registers for Fixed-point Arithmetic 2.1.3. Pre-adder for Fixed-point Arithmetic 2.1.4. Internal Coefficient for Fixed-point Arithmetic 2.1.5. Multipliers for Fixed-point Arithmetic 2.1.6. Adder or Subtractor for Fixed-point Arithmetic 2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic 2.1.8. Systolic Register for Fixed-point Arithmetic 2.1.9. Double Accumulation Register for Fixed-point Arithmetic 2.1.10. Output Register Bank for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic x
2.1.7.1. Dynamic Chainout
2.2. Floating-point Arithmetic x
2.2.1. Input Register Bank for Floating-point Arithmetic 2.2.2. Pipeline Registers for Floating-point Arithmetic 2.2.3. Multipliers for Floating-point Arithmetic 2.2.4. Adder or Subtractor for Floating-point Arithmetic 2.2.5. Output Register Bank for Floating-point Arithmetic 2.2.6. Exception Handling for Floating-point Arithmetic
2.3. Tensor Mode x
2.3.1. Input Register Bank for Tensor Mode 2.3.2. DOT Product Vector Engines for Tensor Mode 2.3.3. Pipeline Registers for Tensor Mode 2.3.4. Fixed-point to Floating-point Converter for Tensor Mode 2.3.5. Cascade Input and Datapath Registers for Tensor Mode 2.3.6. Dynamic Control Multiplexer Bank for Tensor Mode 2.3.7. Accumulator for Tensor Mode 2.3.8. Output Registers for Tensor Mode
2.3.1. Input Register Bank for Tensor Mode x
2.3.1.1. Data Input Feed Preloading Method 2.3.1.2. Side Input Feed Preloading Method
2.3.4. Fixed-point to Floating-point Converter for Tensor Mode x
2.3.4.1. Fixed-point to 32-bit Floating-point Conversion Examples 2.3.4.2. Exception Handling for Floating-point Conversion
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes x
3.1. Operational Modes for Fixed-point Arithmetic 3.2. Operational Modes for Floating-point Arithmetic 3.3. Operational Modes for Tensor Mode
3.1. Operational Modes for Fixed-point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.2. Multiplier Adder Sum Mode x
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode x
3.1.2.1.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode
3.1.4. Systolic FIR Mode x
3.1.4.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.4.2. 18-bit Systolic FIR Mode 3.1.4.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-point Arithmetic x
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions 3.2.2. FP16 Half-precision Floating-point Arithmetic Functions 3.2.3. Multiple Floating-point Variable DSP Blocks Functions
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions x
3.2.1.1. FP32 Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode 3.2.1.4. FP32 Vector One Mode 3.2.1.5. FP32 Vector Two Mode
3.2.2. FP16 Half-precision Floating-point Arithmetic Functions x
3.2.2.1. FP16 Supported Precision Formats 3.2.2.2. Sum of Two FP16 Multiplication Mode 3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode 3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode 3.2.2.5. FP16 Vector One Mode 3.2.2.6. FP16 Vector Two Mode 3.2.2.7. FP16 Vector Three Mode
3.2.3. Multiple Floating-point Variable DSP Blocks Functions x
3.2.3.1. Multiply-Add or Multiply-Subtract Mode 3.2.3.2. Direct Vector Dot Product 3.2.3.3. Complex Multiplication
3.3. Operational Modes for Tensor Mode x
3.3.1. Tensor Floating-point Mode 3.3.2. Tensor Fixed-point Mode 3.3.3. Tensor Accumulation Mode
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations x
4.1. Fixed-point Arithmetic 4.2. Floating-point Arithmetic 4.3. DSP Block Cascade Limit in Agilex™ 5 Devices
4.1. Fixed-point Arithmetic x
4.1.1. Configurations for Input, Pipeline, and Output Registers 4.1.2. Internal Coefficient and Pre-Adder for Fixed-point Arithmetic 4.1.3. Accumulator for Fixed-point Arithmetic 4.1.4. Input Cascade for Fixed-point Arithmetic 4.1.5. Chainout Adder
4.1.1. Configurations for Input, Pipeline, and Output Registers x
4.1.1.1. Restrictions for Input Registers 4.1.1.2. Restrictions for Pipeline Registers 4.1.1.3. Supported Register Configurations per Operation Modes
4.1.4. Input Cascade for Fixed-point Arithmetic x
4.1.4.1. Dynamic Scanin
4.2. Floating-point Arithmetic x
4.2.1. Configurations for Input, Pipeline, and Output Registers 4.2.2. Chainout Adder
4.2.1. Configurations for Input, Pipeline, and Output Registers x
4.2.1.1. FP32 Operation Modes Supported Register Configurations 4.2.1.2. FP16 Operation Mode Supported Register Configurations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References x
5.1. Native Fixed Point DSP Agilex™ FPGA IP Release Information 5.2. Supported Operational Modes 5.3. Maximum Input Data Width for Fixed-point Arithmetic 5.4. Maximum Output Data Width for Fixed-point Arithmetic 5.5. Parameterizing Native Fixed Point DSP IP 5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals 5.7. IP Migration
5.3. Maximum Input Data Width for Fixed-point Arithmetic x
5.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
5.5. Parameterizing Native Fixed Point DSP IP x
5.5.1. Operation Mode Tab 5.5.2. Input Cascade Tab 5.5.3. Pre-adder Tab 5.5.4. Internal Coefficient Tab 5.5.5. Accumulator/Output Chaining 5.5.6. Pipelining 5.5.7. Clear Signal
5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals x
5.6.1. 9 × 9 Sum of 6 Mode Signals 5.6.2. 16 × 16 Complex Multiplier Mode Signals 5.6.3. 18 × 18 Full Mode Signals 5.6.4. 18 × 18 Sum of Two Mode Signals 5.6.5. 18 × 18 Plus 36 Mode Signals 5.6.6. 18 × 18 Systolic Mode Signals 5.6.7. 27 × 27 Mode Signals
6. Multiply Adder Intel® FPGA IP Core References x
6.1. Multiply Adder Intel® FPGA IP Release Information 6.2. Features 6.3. Parameters 6.4. Signals
6.2. Features x
6.2.1. Pre-adder 6.2.2. Systolic Delay Register 6.2.3. Pre-load Constant 6.2.4. Double Accumulator
6.2.1. Pre-adder x
6.2.1.1. Pre-adder Simple Mode 6.2.1.2. Pre-adder Coefficient Mode 6.2.1.3. Pre-adder Input Mode 6.2.1.4. Pre-adder Square Mode 6.2.1.5. Pre-adder Constant Mode
6.3. Parameters x
6.3.1. General Tab 6.3.2. Extra Modes 6.3.3. Multipliers Tab 6.3.4. Preadder Tab 6.3.5. Accumulator Tab 6.3.6. Systolic/Chainout Tab 6.3.7. Pipelining Tab
7. ALTMULT_COMPLEX Intel® FPGA IP Core References x
7.1. ALTMULT_COMPLEX Intel® FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
8. LPM_MULT Intel® FPGA IP Core References x
8.1. LPM_MULT Intel® FPGA IP Release Information 8.2. Features 8.3. Parameters 8.4. Signals
8.3. Parameters x
8.3.1. General Tab 8.3.2. General 2 Tab 8.3.3. Pipelining Tab
9. LPM_DIVIDE (Divider) Intel FPGA IP Core x
9.1. LPM_DIVIDE Intel® FPGA IP Release Information 9.2. Features 9.3. Verilog HDL Prototype 9.4. VHDL Component Declaration 9.5. VHDL LIBRARY_USE Declaration 9.6. Ports 9.7. Parameters
9.7. Parameters x
9.7.1. General Tab 9.7.2. General1 Tab
10. Native Floating Point DSP Agilex™ FPGA IP References x
10.1. Native Floating Point DSP Agilex™ FPGA IP Release Information 10.2. Native Floating Point DSP Agilex™ FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP 10.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals 10.5. IP Migration
10.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP x
10.3.1. General Tab 10.3.2. Registers Tab
10.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals x
10.4.1. FP32 Multiplication Mode Signals 10.4.2. FP32 Addition or Subtraction Mode Signals 10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals 10.4.4. FP32 Multiplication with Accumulation Mode Signals 10.4.5. FP32 Vector One and Vector Two Modes Signals 10.4.6. Sum of Two FP16 Multiplication Mode Signals 10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals 10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals 10.4.9. FP16 Vector One and Vector Two Modes Signals 10.4.10. FP16 Vector Three Mode Signals
11. Native AI Optimized DSP Agilex™ FPGA IP References x
11.1. Native AI Optimized DSP Agilex™ FPGA IP Release Information 11.2. Native AI Optimized DSP Agilex™ FPGA IP Core Supported Operational Modes 11.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP 11.4. Native AI Optimized DSP Agilex™ FPGA IP Core Signals 11.5. IP Migration
11.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP x
11.3.1. Operation Mode Tab 11.3.2. Clock Source Enable/Clear Tab
11.4. Native AI Optimized DSP Agilex™ FPGA IP Core Signals x
11.4.1. Tensor Floating-point Mode Signals 11.4.2. Tensor Fixed-point Mode Signals 11.4.3. Tensor Accumulation Mode Signals
1. Agilex™ 5 Variable Precision DSP Blocks Overview
2. Agilex™ 5 Variable Precision DSP Blocks Architecture
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE (Divider) Intel FPGA IP Core
10. Native Floating Point DSP Agilex™ FPGA IP References
11. Native AI Optimized DSP Agilex™ FPGA IP References
12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide

2.3.1.2. Side Input Feed Preloading Method

The side input feed preloading method preloads the 80-bit weight data and 8-bit shared exponent data into the ping-pong buffers using data_in[87:80] and data_in[95:88] buses. The preloading process takes 12 cycles to complete preloading for one set of ping-pong buffers or 24 cycles to complete the preloading of two sets of ping-pong buffers. The weight and shared exponent data are preloaded independently even if the DSP blocks are cascaded. This enables the tensor computation to continue while the second and subsequent sets are preloaded. The following figure shows the dataflow for side input feed.

Figure 20. Dataflow for Side Input Feed MethodThe feed paths are highlighted in red in this figure.
Figure 21. Side Input Feed Method Timing Diagrams
  1. In cycle 1 to 12, the dynamic control signals are set as follow:
    • load_bb_one = 1’b1 and load_bb_two = 1’b0 to preload the weight and shared exponent data into the first set of ping-pong buffers
    • load_buf_sel = 1’b0 to not switch the ping-pong buffers
  2. In cycle 13 to cycle 24, the DSP block takes the activation data and the shared exponents from data_in[79:0] and shared_exponent[7:0] respectively. The N represents the cycle number for the DSP block to complete loading the activation data and the shared exponents. The load_buf_sel is set to 1’b0 to disable the ping-pong buffers loading. The DSP block takes the loaded weights from the first set of ping-pong buffers for DOT product computations.
  3. Simultaneously, in cycle 13 to 24, the dynamic control signals are set as follow:
    • load_bb_one = 1’b0 and load_bb_two = 1’b1 to preload the weight and shared exponent data into the second set of ping-pong buffers
    • load_buf_sel = 1’b0 to not switch the ping-pong buffers
  4. From cycle N+1 to cycle 2N+1, the DSP block takes the activation data and the shared exponents from data_in[79:0] and shared_exponent[7:0]. The load_buf_sel is set to 1’b1 to switch to the data in the second set of ping-pong buffers for DOT product computations.
  5. The overall process repeats when all the data in the ping-pong buffers have been processed.
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