Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813968
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Variable Precision DSP Blocks Overview 2. Agilex™ 5 Variable Precision DSP Blocks Architecture 3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes 4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations 5. Native Fixed Point DSP Agilex™ FPGA IP Core References 6. Multiply Adder Intel® FPGA IP Core References 7. ALTMULT_COMPLEX Intel® FPGA IP Core References 8. LPM_MULT Intel® FPGA IP Core References 9. LPM_DIVIDE (Divider) Intel FPGA IP Core 10. Native Floating Point DSP Agilex™ FPGA IP References 11. Native AI Optimized DSP Agilex™ FPGA IP References 12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide
1. Agilex™ 5 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Agilex™ 5 Devices
1.2. Supported Operational Modes in Agilex™ 5 Devices x
1.2.1. Fixed-point Arithmetic 1.2.2. Floating-point Arithmetic
2. Agilex™ 5 Variable Precision DSP Blocks Architecture x
2.1. Fixed-point Arithmetic 2.2. Floating-point Arithmetic 2.3. Tensor Mode
2.1. Fixed-point Arithmetic x
2.1.1. Input Register Bank for Fixed-point Arithmetic 2.1.2. Pipeline Registers for Fixed-point Arithmetic 2.1.3. Pre-adder for Fixed-point Arithmetic 2.1.4. Internal Coefficient for Fixed-point Arithmetic 2.1.5. Multipliers for Fixed-point Arithmetic 2.1.6. Adder or Subtractor for Fixed-point Arithmetic 2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic 2.1.8. Systolic Register for Fixed-point Arithmetic 2.1.9. Double Accumulation Register for Fixed-point Arithmetic 2.1.10. Output Register Bank for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic x
2.1.7.1. Dynamic Chainout
2.2. Floating-point Arithmetic x
2.2.1. Input Register Bank for Floating-point Arithmetic 2.2.2. Pipeline Registers for Floating-point Arithmetic 2.2.3. Multipliers for Floating-point Arithmetic 2.2.4. Adder or Subtractor for Floating-point Arithmetic 2.2.5. Output Register Bank for Floating-point Arithmetic 2.2.6. Exception Handling for Floating-point Arithmetic
2.3. Tensor Mode x
2.3.1. Input Register Bank for Tensor Mode 2.3.2. DOT Product Vector Engines for Tensor Mode 2.3.3. Pipeline Registers for Tensor Mode 2.3.4. Fixed-point to Floating-point Converter for Tensor Mode 2.3.5. Cascade Input and Datapath Registers for Tensor Mode 2.3.6. Dynamic Control Multiplexer Bank for Tensor Mode 2.3.7. Accumulator for Tensor Mode 2.3.8. Output Registers for Tensor Mode
2.3.1. Input Register Bank for Tensor Mode x
2.3.1.1. Data Input Feed Preloading Method 2.3.1.2. Side Input Feed Preloading Method
2.3.4. Fixed-point to Floating-point Converter for Tensor Mode x
2.3.4.1. Fixed-point to 32-bit Floating-point Conversion Examples 2.3.4.2. Exception Handling for Floating-point Conversion
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes x
3.1. Operational Modes for Fixed-point Arithmetic 3.2. Operational Modes for Floating-point Arithmetic 3.3. Operational Modes for Tensor Mode
3.1. Operational Modes for Fixed-point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.2. Multiplier Adder Sum Mode x
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode x
3.1.2.1.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode
3.1.4. Systolic FIR Mode x
3.1.4.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.4.2. 18-bit Systolic FIR Mode 3.1.4.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-point Arithmetic x
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions 3.2.2. FP16 Half-precision Floating-point Arithmetic Functions 3.2.3. Multiple Floating-point Variable DSP Blocks Functions
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions x
3.2.1.1. FP32 Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode 3.2.1.4. FP32 Vector One Mode 3.2.1.5. FP32 Vector Two Mode
3.2.2. FP16 Half-precision Floating-point Arithmetic Functions x
3.2.2.1. FP16 Supported Precision Formats 3.2.2.2. Sum of Two FP16 Multiplication Mode 3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode 3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode 3.2.2.5. FP16 Vector One Mode 3.2.2.6. FP16 Vector Two Mode 3.2.2.7. FP16 Vector Three Mode
3.2.3. Multiple Floating-point Variable DSP Blocks Functions x
3.2.3.1. Multiply-Add or Multiply-Subtract Mode 3.2.3.2. Direct Vector Dot Product 3.2.3.3. Complex Multiplication
3.3. Operational Modes for Tensor Mode x
3.3.1. Tensor Floating-point Mode 3.3.2. Tensor Fixed-point Mode 3.3.3. Tensor Accumulation Mode
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations x
4.1. Fixed-point Arithmetic 4.2. Floating-point Arithmetic 4.3. DSP Block Cascade Limit in Agilex™ 5 Devices
4.1. Fixed-point Arithmetic x
4.1.1. Configurations for Input, Pipeline, and Output Registers 4.1.2. Internal Coefficient and Pre-Adder for Fixed-point Arithmetic 4.1.3. Accumulator for Fixed-point Arithmetic 4.1.4. Input Cascade for Fixed-point Arithmetic 4.1.5. Chainout Adder
4.1.1. Configurations for Input, Pipeline, and Output Registers x
4.1.1.1. Restrictions for Input Registers 4.1.1.2. Restrictions for Pipeline Registers 4.1.1.3. Supported Register Configurations per Operation Modes
4.1.4. Input Cascade for Fixed-point Arithmetic x
4.1.4.1. Dynamic Scanin
4.2. Floating-point Arithmetic x
4.2.1. Configurations for Input, Pipeline, and Output Registers 4.2.2. Chainout Adder
4.2.1. Configurations for Input, Pipeline, and Output Registers x
4.2.1.1. FP32 Operation Modes Supported Register Configurations 4.2.1.2. FP16 Operation Mode Supported Register Configurations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References x
5.1. Native Fixed Point DSP Agilex™ FPGA IP Release Information 5.2. Supported Operational Modes 5.3. Maximum Input Data Width for Fixed-point Arithmetic 5.4. Maximum Output Data Width for Fixed-point Arithmetic 5.5. Parameterizing Native Fixed Point DSP IP 5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals 5.7. IP Migration
5.3. Maximum Input Data Width for Fixed-point Arithmetic x
5.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
5.5. Parameterizing Native Fixed Point DSP IP x
5.5.1. Operation Mode Tab 5.5.2. Input Cascade Tab 5.5.3. Pre-adder Tab 5.5.4. Internal Coefficient Tab 5.5.5. Accumulator/Output Chaining 5.5.6. Pipelining 5.5.7. Clear Signal
5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals x
5.6.1. 9 × 9 Sum of 6 Mode Signals 5.6.2. 16 × 16 Complex Multiplier Mode Signals 5.6.3. 18 × 18 Full Mode Signals 5.6.4. 18 × 18 Sum of Two Mode Signals 5.6.5. 18 × 18 Plus 36 Mode Signals 5.6.6. 18 × 18 Systolic Mode Signals 5.6.7. 27 × 27 Mode Signals
6. Multiply Adder Intel® FPGA IP Core References x
6.1. Multiply Adder Intel® FPGA IP Release Information 6.2. Features 6.3. Parameters 6.4. Signals
6.2. Features x
6.2.1. Pre-adder 6.2.2. Systolic Delay Register 6.2.3. Pre-load Constant 6.2.4. Double Accumulator
6.2.1. Pre-adder x
6.2.1.1. Pre-adder Simple Mode 6.2.1.2. Pre-adder Coefficient Mode 6.2.1.3. Pre-adder Input Mode 6.2.1.4. Pre-adder Square Mode 6.2.1.5. Pre-adder Constant Mode
6.3. Parameters x
6.3.1. General Tab 6.3.2. Extra Modes 6.3.3. Multipliers Tab 6.3.4. Preadder Tab 6.3.5. Accumulator Tab 6.3.6. Systolic/Chainout Tab 6.3.7. Pipelining Tab
7. ALTMULT_COMPLEX Intel® FPGA IP Core References x
7.1. ALTMULT_COMPLEX Intel® FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
8. LPM_MULT Intel® FPGA IP Core References x
8.1. LPM_MULT Intel® FPGA IP Release Information 8.2. Features 8.3. Parameters 8.4. Signals
8.3. Parameters x
8.3.1. General Tab 8.3.2. General 2 Tab 8.3.3. Pipelining Tab
9. LPM_DIVIDE (Divider) Intel FPGA IP Core x
9.1. LPM_DIVIDE Intel® FPGA IP Release Information 9.2. Features 9.3. Verilog HDL Prototype 9.4. VHDL Component Declaration 9.5. VHDL LIBRARY_USE Declaration 9.6. Ports 9.7. Parameters
9.7. Parameters x
9.7.1. General Tab 9.7.2. General1 Tab
10. Native Floating Point DSP Agilex™ FPGA IP References x
10.1. Native Floating Point DSP Agilex™ FPGA IP Release Information 10.2. Native Floating Point DSP Agilex™ FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP 10.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals 10.5. IP Migration
10.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP x
10.3.1. General Tab 10.3.2. Registers Tab
10.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals x
10.4.1. FP32 Multiplication Mode Signals 10.4.2. FP32 Addition or Subtraction Mode Signals 10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals 10.4.4. FP32 Multiplication with Accumulation Mode Signals 10.4.5. FP32 Vector One and Vector Two Modes Signals 10.4.6. Sum of Two FP16 Multiplication Mode Signals 10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals 10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals 10.4.9. FP16 Vector One and Vector Two Modes Signals 10.4.10. FP16 Vector Three Mode Signals
11. Native AI Optimized DSP Agilex™ FPGA IP References x
11.1. Native AI Optimized DSP Agilex™ FPGA IP Release Information 11.2. Native AI Optimized DSP Agilex™ FPGA IP Core Supported Operational Modes 11.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP 11.4. Native AI Optimized DSP Agilex™ FPGA IP Core Signals 11.5. IP Migration
11.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP x
11.3.1. Operation Mode Tab 11.3.2. Clock Source Enable/Clear Tab
11.4. Native AI Optimized DSP Agilex™ FPGA IP Core Signals x
11.4.1. Tensor Floating-point Mode Signals 11.4.2. Tensor Fixed-point Mode Signals 11.4.3. Tensor Accumulation Mode Signals
1. Agilex™ 5 Variable Precision DSP Blocks Overview
2. Agilex™ 5 Variable Precision DSP Blocks Architecture
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE (Divider) Intel FPGA IP Core
10. Native Floating Point DSP Agilex™ FPGA IP References
11. Native AI Optimized DSP Agilex™ FPGA IP References
12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide

5.5.1. Operation Mode Tab

Table 54.  Operation Mode Tab
Parameter IP Generated Parameter Value Default Value Description
Please choose the operation mode operation_mode

m9x9_sumof6

complex_mult

m18×18_full

m18×18_sumof2

m18×18_plus36

m18×18_systolic

m27×27

m18×18_full Select the desired operational mode.
1st Multiplier Configuration
Representation format for 'ax' operand signed_max

unsigned

signed

unsigned Specify the representation format for the first multiplier x operand.
Representation format for 'ay' operand signed_may

unsigned

signed

unsigned

Specify the representation format for the first multiplier y operand.
'ax' input bus width ax_width 0–27 —

Specify the width of ax input bus.

For more information about supported input width, refer to the related information.
Enable 'ax' input register ax_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for ax input register.

For more information about clock enable restrictions for input registers, refer to the related information.
'ay' or 'scanin' bus width ay_scan_in_width 1–27 18

Specify the width of ay or scanin input bus.

For more information about supported input width, refer to the related information.
Enable 'ay' or 'scanin' input register ay_scan_in_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for ay or scanin input register.

For more information about clock enable restrictions for input registers, refer to the related information.
2nd Multiplier Configuration
Representation format for 'bx' operand signed_mbx

unsigned

signed

unsigned Specify the representation format for second multiplier x operand.
Representation format for 'by' operand signed_mby

unsigned

signed

unsigned Specify the representation format for second multiplier y operand.

Always select unsigned for m18×18_plus36.

'bx' input bus width bx_width 0–36 18

Specify the width of bx input bus.

For more information about supported input width, refer to the related information.
Enable 'bx' input register bx_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for bx input register.

For more information about clock enable restrictions for input registers, refer to the related information.
'by' input bus width by_width 0–19 18

Specify the width of by input bus.

For more information about supported input width, refer to the related information.
Enable 'by' input register by_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for by input register.

For more information about clock enable restrictions for input registers, refer to the related information.
3rd Multiplier Configuration
Representation format for 'cx' operand signed_mcx

unsigned

signed

unsigned Specify the representation format for third multiplier x operand.

Only m9x9_sumof6 operational mode supports this parameter.

Representation format for 'cy' operand signed_mcy

unsigned

signed

unsigned Specify the representation format for third multiplier y operand.

Only m9x9_sumof6 operational mode supports this parameter.

'cx' input bus width cx_width 0–9 0 Specify the width of cx input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'cx' input register cx_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for cx input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
'cy' input bus width cy_width 0–9 0 Specify the width of cy input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'cy' input register cy_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for cy input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
4th Multiplier Configuration
Representation format for 'dx' operand signed_mdx

unsigned

signed

unsigned Specify the representation format for fourth multiplier x operand.

Only m9x9_sumof6 operational mode supports this parameter.

Representation format for 'dy' operand signed_mdy

unsigned

signed

unsigned Specify the representation format for fourth multiplier y operand.

Only m9x9_sumof6 operational mode supports this parameter.

'dx' input bus width dx_width 0–9 0 Specify the width of dx input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'dx' input register dx_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for dx input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
'dy' input bus width dy_width 0–9 0 Specify the width of dy input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'dy' input register dy_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for dy input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
5th Multiplier Configuration
Representation format for 'ex' operand signed_mex

unsigned

signed

unsigned Specify the representation format for fourth multiplier x operand.

Only m9x9_sumof6 operational mode supports this parameter.

Representation format for 'ey' operand signed_mey

unsigned

signed

unsigned Specify the representation format for fourth multiplier y operand.

Only m9x9_sumof6 operational mode supports this parameter.

'ex' input bus width ex_width 0–9 0 Specify the width of ex input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'ex' input register ex_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for ex input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
'ey' input bus width ey_width 0–9 0 Specify the width of ey input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'ey' input register ey_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for ey input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
6th Multiplier Configuration
Representation format for 'fx' operand signed_mfx

unsigned

signed

unsigned Specify the representation format for fourth multiplier x operand.

Only m9x9_sumof6 operational mode supports this parameter.

Representation format for 'fy' operand signed_mfy

unsigned

signed

unsigned Specify the representation format for fourth multiplier y operand.

Only m9x9_sumof6 operational mode supports this parameter.

'fx' input bus width fx_width 0–9 0 Specify the width of fx input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'fx' input register fx_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for fx input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
'fy' input bus width fy_width 0–9 0 Specify the width of fy input bus.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about supported input width, refer to the related information.
Enable 'fy' input register fy_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for fy input register.

Only m9x9_sumof6 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.
Sub Configuration
Enable 'sub' port enable_sub

No

Yes

No

Select to enable sub port.

The sub port is an input signal that can be used dynamically to subtract the output of the top multiplier from the output of the bottom multiplier.

Only available for the following operation modes:
  • m18×18_full
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic

For more information about the sub port, refer to the related information.

Enable 'sub' input register sub_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for sub input register.
Only available for the following operation modes:
  • m18×18_full
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic

For more information about clock enable restrictions for input registers, refer to the related information.
Enable 'sub systolic' register sub_systolic_reg

no_reg

ena0

ena1

ena2

no_reg

Only supported in m18x18_systolic mode.

Must be enabled when "sub" port is used.
Output 'result' Configuration
'resulta' output bus width result_a_width 1–64 37 Specify the width of resulta output bus.
'resultb' output bus width result_b_width 0–37 37 Specify the width of resultb output bus.

Only available for m18x18_full operation mode.

Enable output register output_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for resulta and resultb output register.
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