Visible to Intel only — GUID: rkn1690740218821
Ixiasoft
1. Agilex™ 5 Variable Precision DSP Blocks Overview
2. Agilex™ 5 Variable Precision DSP Blocks Architecture
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE (Divider) Intel FPGA IP Core
10. Native Floating Point DSP Agilex™ FPGA IP References
11. Native AI Optimized DSP Agilex™ FPGA IP References
12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide
2.1.1. Input Register Bank for Fixed-point Arithmetic
2.1.2. Pipeline Registers for Fixed-point Arithmetic
2.1.3. Pre-adder for Fixed-point Arithmetic
2.1.4. Internal Coefficient for Fixed-point Arithmetic
2.1.5. Multipliers for Fixed-point Arithmetic
2.1.6. Adder or Subtractor for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
2.1.8. Systolic Register for Fixed-point Arithmetic
2.1.9. Double Accumulation Register for Fixed-point Arithmetic
2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2.1. Input Register Bank for Floating-point Arithmetic
2.2.2. Pipeline Registers for Floating-point Arithmetic
2.2.3. Multipliers for Floating-point Arithmetic
2.2.4. Adder or Subtractor for Floating-point Arithmetic
2.2.5. Output Register Bank for Floating-point Arithmetic
2.2.6. Exception Handling for Floating-point Arithmetic
2.3.1. Input Register Bank for Tensor Mode
2.3.2. DOT Product Vector Engines for Tensor Mode
2.3.3. Pipeline Registers for Tensor Mode
2.3.4. Fixed-point to Floating-point Converter for Tensor Mode
2.3.5. Cascade Input and Datapath Registers for Tensor Mode
2.3.6. Dynamic Control Multiplexer Bank for Tensor Mode
2.3.7. Accumulator for Tensor Mode
2.3.8. Output Registers for Tensor Mode
3.2.2.1. FP16 Supported Precision Formats
3.2.2.2. Sum of Two FP16 Multiplication Mode
3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode
3.2.2.5. FP16 Vector One Mode
3.2.2.6. FP16 Vector Two Mode
3.2.2.7. FP16 Vector Three Mode
5.1. Native Fixed Point DSP Agilex™ FPGA IP Release Information
5.2. Supported Operational Modes
5.3. Maximum Input Data Width for Fixed-point Arithmetic
5.4. Maximum Output Data Width for Fixed-point Arithmetic
5.5. Parameterizing Native Fixed Point DSP IP
5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals
5.7. IP Migration
10.4.1. FP32 Multiplication Mode Signals
10.4.2. FP32 Addition or Subtraction Mode Signals
10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals
10.4.4. FP32 Multiplication with Accumulation Mode Signals
10.4.5. FP32 Vector One and Vector Two Modes Signals
10.4.6. Sum of Two FP16 Multiplication Mode Signals
10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals
10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals
10.4.9. FP16 Vector One and Vector Two Modes Signals
10.4.10. FP16 Vector Three Mode Signals
Visible to Intel only — GUID: rkn1690740218821
Ixiasoft
5.6.1. 9 × 9 Sum of 6 Mode Signals
Figure 61. 9 × 9 Sum of 6 Mode Signals
Signal Name | Type | Width | Description |
---|---|---|---|
ax[8:0] | Input | 9 | Input data bus to first multiplier. |
ay[8:0] | Input | 9 | Input data bus to first multiplier. When pre-adder is enabled, these signals are served as input to the top pre-adder. |
bx[8:0] | Input | 9 | Input data bus to second multiplier. |
by[17:0] | Input | 9 | Input data bus to second multiplier. When pre-adder is enabled, these signals are served as input to the bottom pre-adder. |
cx[8:0] | Input | 9 | Input data bus to third multiplier. |
cy[8:0] | Input | 9 | |
dx[8:0] | Input | 9 | Input data bus to third multiplier |
dy[8:0] | Input | 9 | |
ex[8:0] | Input | 9 | Input data bus to fifth multiplier |
ey[8:0] | Input | 9 | |
fx[8:0] | Input | 9 | Input data bus to sixth multiplier |
fy[8:0] | Input | 9 | |
resulta[63:0] | Output | 64 | Output data bus. |
Signal Name | Type | Width | Description |
---|---|---|---|
clk[0] | Input | 1 | Input clock for all registers. |
ena[2:0] | Input | 3 | Clock enable signals for all registers. These signals are active-High. |
clr[1:0] | Input | 2 | These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of clear signal parameter. These signals are active-High. By default, this signal is low. For more information about clock enable restrictions for input registers, refer to the related information. |
Signal Name | Type | Width | Description |
---|---|---|---|
disable_chainout | Input | 1 | Dynamic input signal to enable dynamic chainout feature. You can change the value of this signal during run-time. You must connect the chainout output bus to the next DSP block in order to use this signal.
|
accumulate | Input | 1 | Input signal to enable or disable the accumulator feature. You can change the value of this signal during run-time.
|
loadconst | Input | 1 | Input signal to enable or disable the load constant feature. You can change the value of this signal during run-time.
|