MIPI CSI-2 Intel® FPGA IP Design Example User Guide

ID 813931
Date 10/07/2024
Public

2. MIPI CSI-2 Intel® FPGA IP Design Example

The MIPI CSI-2 Intel® FPGA IP has two design example variants for Agilex™ 5 devices, namely MIPI CSI-2 RX+TX and MIPI CSI-2 RX-only.
Features Included in the MIPI CSI-2 Example Design
Feature Support Range
Direction RX, TX
D-PHY Lanes 1, 2, 4, 8
Bits per Lane 16
Pixels in parallel 1, 2, 4
Video Data Format YUV420 8-bit(legacy), YUV420 8-bit, YUV420 10-bit, YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444, RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW16, RAW20 & RAW24
Buffer Depth 128, 256, 512, 1024, 2048, 4096, 8192, 16384