MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Design 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. MIPI CSI-2 Design Components 2.4.2. MIPI CSI-2 IP Design Example Reset Scheme 2.4.3. MIPI CSI-2 IP Design Example Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. PHY-Protocol Interface (PPI) Loopback 2.5.5.3. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5. Simulation

The MIPI CSI-2 IP design example simulation demonstrates the correct way to drive data onto the AXI4-Stream of the CSI-2 TX and demonstrates correctly receiving data from the AXI4-Stream of the CSI-2 RX.

The simulation is designed to run either in video mode which has the AXI4-Stream complying with the Intel Video Streaming Protocol, or in passthrough mode that uses the MIPI CSI-2 protocol to define how the data is presented on the AXI4-Stream

Both full and fast simulation can run when you select Video for Video Interface Mode, which has the AXI4-Stream complying with the Intel Video Streaming Protocol. Fast simulations also support Passthrough for Video Interface Mode, which passes data in the MIPI CSI-2 byte stream form on the AXI-Stream interfaces.

The simulation generates the correct signals and data on the AXI4-Stream input of the CSI-2 TX. This then passes through the CSI-2 TX and out of the PPI of the CSI-2 TX.

When you select Fast simulation, the PPI then loops back into the PPI of the CSI-2 RX. The data passes through the CSI-2 RX and then out of the AXI4-Stream. The simulation then checks the signals and data on the AXI4-Stream of the CSI-2 RX to make sure they match what is expected. You can view the AXI4-Stream video interfaces operating while simulating rapidly..

When you select Full simulation, the TX PPI connects to the D-PHY TX. The D-PHY signals produced loop back into the D-PHY RX, with the RX PPI signals connected to CSI-2 RX. This simulation shows the full system datapath including external IOs, which is the external MIPI D-PHY signalling in a hardware system.


Section Content
Data Signal Checking
Verification
Display Messages
Waveform Plotting
Structure
Known Limitations

Level Two Title