MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Design 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. MIPI CSI-2 Design Components 2.4.2. MIPI CSI-2 IP Design Example Reset Scheme 2.4.3. MIPI CSI-2 IP Design Example Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. PHY-Protocol Interface (PPI) Loopback 2.5.5.3. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5.1. Data Signal Checking

MIPI CSI-2 is a transport protocol, and it is expected that the output of the CSI-2 RX should perfectly match the input of the CSI-2 TX. A time delay is expected between the input and the output, and this delay is variable. The other exception is that backpressure may result in different signal handshaking of tvalid and tready. However, the valid data beats are expected to match.

Rules that give simulation failure:
  • Out-of-order transmission is not allowed and not possible in MIPI CSI-2.
  • This simulation does not allow for data corruption. Corruption may occur when running in hardware due to signal integrity issue and or an allowable BER due to electrical characteristics of the transmission lines.
  • The simulation does not allow for data loss. All data sent must be received or the simulation fails.
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