2.3.1. Design Components
Component | Description |
---|---|
Triple-Speed Ethernet Intel® FPGA IP | The Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) is instantiated with the following configuration:
|
Client Logic | Generates and monitors packets sent or received through the IP. |
JTAG to Avalon® memory-mapped interface Address Decoder | Convert JTAG Signals for Avalon® memory-mapped interface. |
IOPLL | Generates 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet. |
GTS Reset Sequencer | Supports GTS Transceiver for Triple-Speed Ethernet IP. |
System PLL | Generates 322.265625 MHz or 644.53125 MHz PLL clock for GTS transceiver. |
Note: Data Clocking mode supports both PMA and SYSPLL. SYSPLL support is added with existing preset setting by default. If PMA mode is required, you have to select it from the parameter editor.