Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813899
Date 7/08/2024
Public

1.4. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/intel_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.
  4. After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory. Follow these steps to program the hardware design example on the Agilex™ 5 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) to which your Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.