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Ixiasoft
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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Ixiasoft
2.1. Features
- Generates the design example for Triple-Speed Ethernet MAC 2XTBI with Internal FIFO and PCS with GTS PMA.
- Generates traffic at the transmit path and validates received data through the GTS transceiver serial loopback.
- TX and RX serial loopback mode.
- Supports external loopback.
- Supports only a single port.
- Supports packet statistics report on both MAC transmitter and MAC receiver.
- Basic packet checking capabilities of traffic monitor.