Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813899
Date 7/08/2024
Public

2.1. Features

  • Generates the design example for Triple-Speed Ethernet MAC 2XTBI with Internal FIFO and PCS with GTS PMA.
  • Generates traffic at the transmit path and validates received data through the GTS transceiver serial loopback.
  • TX and RX serial loopback mode.
  • Supports external loopback.
  • Supports only a single port.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Basic packet checking capabilities of traffic monitor.