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1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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2.6. Interface Signals
Signal | Direction | Description |
---|---|---|
pll_refclk0 | Input | 156.25 MHz reference clock used for the rx_cdr_refclk and tx_pll_refclk in the GTS Direct PHY IP. It is also an input clock for the GTS System Clock IP. |
reg_clk | Input | 100 MHz clock for configuring CSR registers and reference clock to IOPLL. It also acts as an input for reconfig_clk. |
tx_serial_data | Output | Positive signal for the transmitter serial data. |
tx_serial_data_n | Output | Negative signal for the transmitter serial data. |
rx_serial_data | Input | Positive signal for the receiver serial data. |
rx_serial_data_n | Input | Negative signal for the receiver serial data. |