Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813899
Date 7/08/2024
Public

2.6. Interface Signals

Table 6.  Interface Signals for 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
Signal Direction Description
pll_refclk0 Input

156.25 MHz reference clock used for the rx_cdr_refclk and tx_pll_refclk in the GTS Direct PHY IP. It is also an input clock for the GTS System Clock IP.

reg_clk Input 100 MHz clock for configuring CSR registers and reference clock to IOPLL.

It also acts as an input for reconfig_clk.

tx_serial_data Output Positive signal for the transmitter serial data.
tx_serial_data_n Output Negative signal for the transmitter serial data.
rx_serial_data Input Positive signal for the receiver serial data.
rx_serial_data_n Input Negative signal for the receiver serial data.