Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.3.1. Design Components

Table 5.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP

The Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
    • Interface: MII/GMII
    • Use internal FIFO: Selected
    • Number of ports: 1
    • Transceiver type: GTS
  • MAC Options:
    • Enable local loopback on MII/GMII: Not selected
    • Enable supplemental MAC unicast addresses: Not selected
    • Include statistics counters: Selected
    • Enable 64-bit statistics byte counters: Not selected
    • Include multicast hashtable: Not selected
    • Align packet headers to 32-bit boundary: Not selected
    • Enable full-duplex flow control: Not selected
    • Enable VLAN detection: Not selected
    • Enable magic packet detection: Selected
    • Enable MAC 10/100 half duplex support: Not selected
  • FIFO Options:
    • Width: 32 bits
    • Depth:
      • Transmit: 4096 x 32 bits
      • Receive: 4096 x 32 bits
  • PCS/Transceiver Options:
    • PCS Options:
      • Enable SGMII bridge: Selected
      • PHY ID (32 bit): 0x01010101
    • GTS Mono Transceiver Options:
      • Enable transceiver dynamic reconfiguration: Selected
      • Data clocking mode: System PLL
      • System PLL Frequency: 322.26560
      • Enable PMA Avalon Interface: Not selected
Client Logic Generates and monitors packets sent or received through the IP.
JTAG to Avalon® memory-mapped interface Address Decoder Convert JTAG Signals for Avalon® memory-mapped interface.
IOPLL Generates 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet.
GTS Reset Sequencer Supports GTS Transceiver for Triple-Speed Ethernet IP.
System PLL Generates 322.265625 MHz or 644.53125 MHz PLL clock for GTS transceiver.
Note: Data Clocking mode supports both PMA and SYSPLL. SYSPLL support is added with existing preset setting by default. If PMA mode is required, you have to select it from the parameter editor.
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