Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813899
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 5.0.0
  • Updated the description in the Quick Start Guide topic.
  • Updated Development Stages for the Design Example figure.
  • Added a note about the Agilex™ 5 D-Series FPGAs and SoCs support in the Quick Start Guide topic.
  • Updated Directory Structure for the Design Example figure.
  • Updated Testbench File Description table.
  • Updated Generating the Design Example topic to include the steps to select the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) target development kit.
  • Updated Parameters in the Example Design Tab table.
  • Removed VCS* from Steps to Simulate the Testbench table.
  • Added Compiling and Configuring the Design Example in Hardware topic.
  • Updated the following for 10/100/1000 ethernet MAC design example with 1000BASE-X/SGMII 2XTBI PCS with GTS transceiver:
    • Features topic.
    • Hardware and Software Requirements topic.
    • Block Diagram—10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver.
    • Updated PCS/Transceiver Options in the Design Components table.
    • Updated Block Diagram of the 10/100/1000Mb Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver Simulation Testbench figure.
    • Added Hardware Testing, Test Procedure topic.
  • Updated description for pll_refclk0 and reg_clk signals in the Interface Signals for 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver table.
2024.04.01 24.1 4.0.0 Initial release.
Level Two Title